Specifications

C–4 SROM Initialization
Subject to Change – 17 January 1997
Memory Initialization
C.4 Memory Initialization
Eight consecutive row address strobe (RAS) cycles are performed to the system
memory bank to “wake up” the DRAMs. This is done by reading the bank eight
times. The caches are disabled at this point so the read data goes directly to the
DRAMs (except for the Scache, which cannot be turned off).
Good data parity is ensured by writing all memory locations. This is done by
rewriting the full contents of memory with the same data. Reading before writing
memory lengthens the time to initialize data parity, however, it conserves the
memory state for debugging purposes.
C.5 Bcache Initialization
The Bcache is initialized by the following steps:
1. Set the BC_CONTROL register in the CPU to ignore parity/ECC reporting.
2. Turn on the Bcache in the 21164 microprocessor and the CIA.
3. Sweep the Bcache with read operations at cache-block increments.
4. Reenable error reporting.
5. Clear error registers.
When the system is powered up, the Bcache contains UNPREDICTABLE data in the
tag RAMs. As the Bcache is swept for initialization, the old blocks (referred to as
dirty-victim blocks) are written back to main memory. These victim write operations
will occur based on the tag address (tag), which stores the upper part of the address
location for the dirty blocks of memory.
Because the tags are unpredictable, the victim write operations could occur to
UNPREDICTABLE addresses. Therefore, these write operations could be attempted
to nonexistent memory. Should this happen, the transaction would complete and an
error would be reported. Therefore, reporting of all nonexistent memory errors in the
CIA must be turned off prior to sweeping.