Specifications

17 January 1997 – Subject to Change
I/O Space Address Maps B–17
Hardware-Specific and Miscellaneous Register Space
B.6.3 CIA PCI Address Translation Map Space
CIA PCI address translation map space occupies physical addresses 87.6000.0000
through 87.6FFF.FFFF. Table B–13 lists all the CIA chip’s PCI address translation
registers.
MBAA RW 87.5000.0880 Memory base address register 10
MBAC RW 87.5000.0900 Memory base address register 12
MBAE RW 87.5000.0980 Memory base address register 14
TMG0 RW 87.5000.0B00 Memory timing information base register 0
TMG1 RW 87.5000.0B40 Memory timing information base register 1
TMG2 RW 87.5000.0B80 Memory timing information base register 2
Table B–13 PCI Address Translation Registers
Register Type Address Description
TBIA WO 87.6000.0100 Scatter-gather translation buffer invalidate
register
W0_BASE RW 87.6000.0400 Window base 0 register
W0_MASK RW 87.6000.0440 Window mask 0 register
T0_BASE RW 87.6000.0480 Translated base 0 register
W1_BASE RW 87.6000.0500 Window base 1 register
W1_MASK RW 87.6000.0540 Window mask 1 register
T1BASE RW 87.6000.0580 Translated base 1 register
W2_BASE RW 87.6000.0600 Window base 2 register
W2_MASK RW 87.6000.0640 Window mask 2 register
T2_BASE RW 87.6000.0680 Translated base 2 register
W3_BASE RW 87.6000.0700 Window base 3 register
W3_MASK RW 87.6000.0740 Window mask 3 register
T3_BASE RW 87.6000.0780 Translated base 3 register
W_DAC RW 87.6000.07C0 Window DAC register
Table B–12 (Continued) CIA Memory Control Registers
Register Type Address Description