Specifications

B–12 I/O Space Address Maps
Subject to Change – 17 January 1997
PCI Dense Memory Space
All flash ROM accesses (except for read operations) require two bus cycles. During
the first cycle, register data is written to set up the registers. During the second cycle,
the read or write transaction performs the operation desired. For more information
about reading, erasing, and writing the flash ROM, see the Intel Flash Memory
document.
Accessing the flash ROM registers requires byte access, which is only possible
through use of PCI sparse memory space. The AlphaPC 164 flash ROM resides in
PCI memory address range FFF8.0000 to FFFF.FFFF. See Section B.2.2 for
information about accessing this address range through sparse memory space.
1
X = Any byte within the flash ROM address range.
2
BA = Target address within the block being erased.
3
WA = Target address of write transaction to memory.
Table B–8 Flash ROM Configuration Registers
Offset
Data Written on
First Access Register
X
1
FF Read array/reset
X 90 Intelligent identifier
X 70 Read status
X50 Clear status
BA
2
20 Erase setup/confirm
X B0 Erase suspend/resume
WA
3
40 Byte write setup/write
WA 10 Alternate byte write setup/write