Specifications

17 January 1997 – Subject to Change
I/O Space Address Maps B–7
PCI Sparse I/O Space
00D 85.C000.01A0 DMA1 master clear
00E 85.C000.01C0 DMA1 clear mask
00F 85.C000.01E0 DMA1 read/write all mask register bits
020 85.C000.0400 INT 1 control
021 85.C000.0420 INT 1 mask
040 85.C000.0800 Timer counter 1 - counter 0 count
041 85.C000.0820 Timer counter 1 - counter 1 count
042 85.C000.0840 Timer counter 1 - counter 2 count
043 85.C000.0860 Timer counter 1 - command mode
060 85.C000.0C00 Reset Ubus IRQ12
061 85.C000.0C20 NMI status and control
070 85.C000.0E00 CMOS RAM address and NMI mask
078–07B 85.C000.0F18 BIOS timer
080 85.C000.1000 DMA page register reserved
081 85.C000.1020 DMA channel 2 page
082 85.C000.1040 DMA channel 3 page
083 85.C000.1060 DMA channel 1 page
084 85.C000.1080 DMA page register reserved
085 85.C000.10A0 DMA page register reserved
086 85.C000.10C0 DMA page register reserved
087 85.C000.10E0 DMA channel 0 page
088 85.C000.1100 DMA page register reserved
089 85.C000.1120 DMA channel 6 page
08A 85.C000.1140 DMA channel 7 page
08B 85.C000.1160 DMA channel 5 page
08C 85.C000.1180 DMA page register reserved
Table B–5 (Continued) SIO Bridge Operating Register Address Space Map
Offset Address Register