Specifications

B–6 I/O Space Address Maps
Subject to Change – 17 January 1997
PCI Sparse I/O Space
B.2.1.4 Interrupt Control PLD Addresses
Table B–4 lists the registers and memory addresses for the interrupt control
programmable logic device (PLD).
B.2.2 PCI Sparse I/O Space-Region B
PCI sparse I/O space, Region B, occupies physical addresses 85.C000.0000 through
85.FFFF.FFFF. This region includes the PCI-to-ISA bridge operating register
address space as well as the operating registers for any optional PCI plug-in boards.
Table B–5 is a map of the SIO PCI-to-ISA bridge operating address space.
Table B–4 Interrupt Control PLD Addresses
Offset Physical Address Register
x804 85.8001.0080 Interrupt status/interrupt mask 1
x805 85.8001.00A0 Interrupt status/interrupt mask 2
x806 85.8001.00C0 Interrupt status/interrupt mask 3
Table B–5 SIO Bridge Operating Register Address Space Map
Offset Address Register
000 85.C000.0000 DMA1 CH0 base and current address
001 85.C000.0020 DMA1 CH0 base and current count
002 85.C000.0040 DMA1 CH1 base and current address
003 85.C000.0060 DMA1 CH1 base and current count
004 85.C000.0080 DMA1 CH2 base and current address
005 85.C000.00A0 DMA1 CH2 base and current count
006 85.C000.00C0 DMA1 CH3 base and current address
007 85.C000.00E0 DMA1 CH3 base and current count
008 85.C000.0100 DMA1 status and command
009 85.C000.0120 DMA1 write request
00A 85.C000.0140 DMA1 write single mask bit
00B 85.C000.0160 DMA1 write mode
00C 85.C000.0180 DMA1 clear byte pointer