Specifications

17 January 1997 – Subject to Change
System Address Mapping A–43
PCI-to-Physical Memory Addressing
•
The MAR1, 2, and 3 registers enable various BIOS regions.
•
The MCSCON (control) register enables the mem_cs_l decode logic, and in
addition, selects a number of regions (0KB to 512KB).
Figure A–21 Memory Chip Select Signal (mem_cs_l) Decode Area
As shown in Figure A–22, PCI window 0 in the CIA can be enabled to accept the
mem_cs_l signal as the PCI memory decode signal. With this path enabled, the PCI
window-hit logic simply uses the mem_cs_l signal. For example, if mem_cs_l is
asserted, then a PCI window 0 hit occurs and the dev_sel_l signal is asserted on the
PCI.
4GB
512MB Max
16MB
Main Memory Hole
1MB
1MB-64KB
VGA Memory
(A0000-BFFF)
512KB
MCSTOM
MCSTOH
MCSBOH
MCSCON
MAR1,2,3
MCSCON
MCSCON
LJ-04279.AI5
BIOS Area
Hole
Hole