Specifications

A–42 System Address Mapping
Subject to Change – 17 January 1997
PCI-to-Physical Memory Addressing
A.4.4.1 PCA Compatibility Addressing and Holes
The peripheral component architecture (PCA) allows certain ISA devices to respond
to hardwired memory addresses. An example is a VGA graphics device that has its
frame buffer located in memory address region A0000-BFFFF. Such devices
“pepper” memory space with holes that are collectively known as peripheral
component architecture compatibility holes.
The PCI-to-ISA bridge decodes PCI addresses and generates a signal, mem_cs_l,
that takes into account the various compatibility holes.
A.4.4.2 Memory Chip Select Signal mem_cs_l
The PCI-to-ISA bridge provides address decode logic with attributes (such as read
only, write only, VGA frame buffer, memory holes, and BIOS shadowing) to help
manage the ISA memory map and peripheral component architecture compatibility
holes.
This is known as main memory decoding in the PCEB chip, and results in the
generation of the memory chip select (mem_cs_l) signal. One exception is the VGA
memory hole region that never asserts mem_cs_l. If enabled, the CIA uses
mem_cs_l with W0_BASE.
In Figure A–21, the two main holes are lightly shaded, while the mem_cs_l range is
darkly shaded.
The mem_cs_l range of Figure A–21 is subdivided into several portions (such as the
BIOS area) that are individually enabled/disabled using CSRs as listed here:
•
The MCSTOM (top-of-memory) register has 2MB granularity and can be
programmed to select the regions from 1MB up to 512MB.
•
The MCSTOH (top-of-hole) and MCSBOH (bottom-of-hole) registers define a
memory hole region where mem_cs_l is not selected. The granularity of the hole
is 64KB.
Table A–13 PCI Window Power-Up Configuration
PCI Window Assignment Size Comments
0 Scatter-Gather 8MB Not used by firmware.
mem_cs_l
disabled.
1 Direct Mapped 1GB Mapped to 0GB to 1GB of main memory.
2 Disabled
——
3 Disabled
——