Specifications

17 January 1997 – Subject to Change
System Address Mapping A–39
PCI-to-Physical Memory Addressing
Figure A–19 shows the entire translation process, from PCI address to physical
address, on a window that implements scatter-gather. The MSB from the PCI
address column of Table A–12 equals n-1. Both paths are indicated; the path for a
TLB hit is to the right, and the path for a TLB miss is to the left. The scatter-gather
TLB is shown in a slightly simplified but functionally equivalent form.
Scatter-Gather TLB Hit Process
The process for a scatter-gather TLB hit is as follows:
The window-compare logic determines if the PCI address has hit in one of the
four windows, and Wn_BASE[Wn_BASE_SG] determines if the scatter-gather
path should be taken. If window 3 has DAC mode enabled, and the PCI cycle is
a DAC cycle, then a further comparison is made between the high-order PCI bits
and W_DAC.
Address bits ad<31:13> are sent to the TLB associative tag together with the
DAC hit indication. If the address and DAC bits match in the TLB, the
corresponding 8KB page 21164 memory address is read out of the TLB. If the
data entry is valid, then a TLB hit occurs and this page address is concatenated
with ad<12:2> to form the physical memory address. If the data entry is invalid,
or if the TAG compare fails, then a TLB miss occurs.
Scatter-Gather TLB Miss Process
The process for a scatter-gather TLB miss is as follows:
The relevant bits of the PCI address (as determined by Wn_MASK) are
concatenated with the relevant Tn_BASE bits to form the address used to access
the scatter-gather PTE from a table located in main memory.
Scatter-gather PTE<20:1> are used to generate the page address that is appended
to the page offset to generate the physical memory address.
At this point, the TLB is also updated (round-robin algorithm) with the four PTE
entries that correspond to the 32KB PCI page 21164 memory address that first
missed the TLB. The tag portion of the TLB is loaded with this PCI page
address, and the DAC bit is set if this PCI cycle is a DAC cycle.
If the requested PTE is marked invalid (bit 0 clear), then a TLB invalid entry
exception is taken.