Specifications

A–38 System Address Mapping
Subject to Change – 17 January 1997
PCI-to-Physical Memory Addressing
Figure A–18 Scatter-Gather Associative TLB
Each time an incoming PCI address hits in a PCI target window that has scatter-
gather enabled, ad<31:15> are compared with the 32KB PCI page address in the
TLB tag. If a match is found, the required 21164 page address is one of the four
items provided by the data in the matching TLB entry. Address bits ad<14:13>
select the correct 8KB page address from the four addresses fetched.
With a TLB hit, the scatter-gather map table lookup in memory is avoided, resulting
in enhanced performance. If no match is found in the TLB, the scatter-gather map
lookup is performed and four PTE entries are fetched and written over an existing
entry in the TLB. The TLB entry to be replaced is determined by a round-robin
algorithm on the “unlocked” entries. Coherency of the TLB is maintained by
software write transactions (invalidates) to the translation buffer invalidate all
(TBIA) register.
The TAG portion of the TLB entry contains a DAC flag to indicate that PCI tag
address bits <31:15> correspond to a 64-bit DAC address. Only one bit is required
instead of the high-order PCI address bits ad<39:32>, because only window 3 is
assigned to a DAC cycle, and the window-hit logic has already performed a
comparison of the high-order address bits against W_DAC.
DAC
Cycle
PCI
Address
<31:15>
8KB CPU Page Address
Hit
Physical memory
Dword Address
Memory Page
Address<32:13>
PCI
Address<12:2>
PCI Address<14:13>
Index
D A T A
TAG
LJ04276A.AI5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V