Specifications

17 January 1997 – Subject to Change
System Address Mapping A–37
PCI-to-Physical Memory Addressing
A.4.3.1 Scatter-Gather Translation Lookaside Buffer (TLB)
An 8-entry TLB is provided in the CIA for scatter-gather PTEs. The TLB is a
fully-associative cache and holds the eight most recent scatter-gather map lookups.
Four of these entries can be “locked,” preventing their displacement by the hardware
TLB-miss handler. Each of the eight TLB entries holds a PCI address for the tag, and
four consecutive 8KB page addresses as the TLB data, as shown in Figure A–18.
1
Unused bits of T
n
_BASE must be zero for correct operation.
Table A–12 Scatter-Gather Mapped PCI Target Address Translation
Scatter-Gather Map Address<33:3>
W_MASK<31:20> Window Size
S-G Map
Table Size T
n
_Base
1
PCI Address
0000 0000 0000 1MB 1KB <32:10> <19:13>
0000 0000 0001 2MB 2KB <32:11> <20:13>
0000 0000 0011 4MB 4KB <32:12> <21:13>
0000 0000 0111 8MB 8KB <32:13> <22:13>
0000 0000 1111 16MB 16KB <32:14> <23:13>
0000 0001 1111 32MB 32KB <32:15> <24:13>
0000 0011 1111 64MB 64KB <32:16> <25:13>
0000 0111 1111 128MB 128KB <32:17> <26:13>
0000 1111 1111 256MB 256KB <32:18> <27:13>
0001 1111 1111 512MB 512KB <32:19> <28:13>
0011 1111 1111 1GB 1MB <32:20> <29:13>
0111 1111 1111 2GB 2MB <32:21> <30:13>
1111 1111 1111 4GB 4MB <32:22> <31:13>