Specifications

A–36 System Address Mapping
Subject to Change – 17 January 1997
PCI-to-Physical Memory Addressing
Each scatter-gather map entry maps an 8KB page of PCI address space into an 8KB
page of 21164 address space. This offers a number of advantages to software such
as:
•
Performance—ISA devices map to the lower 16MB of memory. The Windows
NT operating system currently copies data from this part of memory to user
space. The scatter-gather map avoids this copy operation.
•
Address management—User I/O buffers might not be physically contiguous or
contained within a page. Without scatter-gather maps, software has to manage
the scattered nature of the user buffer.
In PCA, the term scatter-gather is not an address translation scheme, but instead, is
used to signify a DMA transfer list. An element of this transfer list contains the
DMA address and the number of data items to transfer. The DMA device fetches
each item of the list until the list is empty. Many of the PCI devices, such as the
PCI-to-ISA bridge, support this form of scatter-gather process.
Each scatter-gather PTE is a quadword and has a valid bit in PTE<0> as shown in
Figure A–17. Page address bit <13> is at PTE<1>.
Figure A–17 Scatter-Gather PTE Format
Because the CIA implements only valid memory addresses up to 8GB, scatter-gather
PTE bits <63:21> must be set to zero. PTE bits <20:1> are used to generate the
physical page address. This address is appended to ad<12:5> of the incoming PCI
address to generate the memory address.
The size of the scatter-gather map table is determined by the size of the PCI target
window defined by Wn_MASK, as shown in Table A–12. The number of entries is
the window size divided by the page size (8KB). The size of the table is simply the
number of entries multiplied by 8 bytes.
The scatter-gather map table address is obtained from Tn_BASE and the PCI
address, as shown in Table A–12.
63 012021 00
LJ-04275.AI
PAGE_ADDRESS<32:13>
VALID
MBZ