Specifications

17 January 1997 – Subject to Change
System Address Mapping A–31
PCI-to-Physical Memory Addressing
A.4.1.1 PCI Device Address Space
A PCI device specifies the amount of memory space it requires by using base
registers in its configuration space. The registers are implemented such that the
address space consumed by the device is a power of two in size, and is
NATURALLY ALIGNED on the size of the space consumed.
A PCI device need not use all of the address range that it consumes, that is, the size
of the PCI address window defined by the base address. Also, a PCI device need not
respond to unused portions of the address space.
Note:
The one exception to this is a PCI bridge that requires two additional
registers (the base and limit address registers). These registers specify
the address space that the PCI bridge will respond to in transactions.
A PCI bridge responds to all addresses in the range: base ≤ address < limit.
These base and limit address registers are initialized by POST code at power-up. The
CIA, as a PCI host-bridge device, does not have base and limit registers. Host
bridges, because they are under system control, do not have to operate within the
rules for other PCI devices. The CIA does respond to all the addresses within the
four windows.
A.4.1.2 Address Mapping Example
Figure A–14 shows how the DMA address ranges of a number of PCI devices are
within the PCI window ranges. PCI devices are allowed to have multiple DMA
address ranges, like device 2.