Specifications

A–26 System Address Mapping
Subject to Change – 17 January 1997
21164 Address Space
•
Bytes 0 and 1 contain the encoded message.
•
Bytes 2 and 3 contain a message-dependent (optional) data field.
A read to address range 87.2000.0000 to 87.3FFF.FFFF will result in an interrupt
acknowledge cycle on the PCI returning the vector data, which is provided by the
PCI-to-ISA bridge, to the 21164 microprocessor.
A.3.4.3 Hardware-Specific and Miscellaneous Register Space
Hardware-specific and miscellaneous register space is located in the range
87.4000.0000 to 87.FFFF.FFFF. Table A–8 lists the regions, with hardware
registers, within this space.
A.3.5 Byte/Word PCI Space
The 21164 microprocessor supports byte/word instructions that allow software to
access I/O space with byte granularity without using sparse space. Byte/word space
is divided into four regions as shown in Figure A–13.
1
This address space is a hardware-specific variant of sparse space encoding. For the CSRs,
addr<27:6>
specify a longword address where
addr<5:0>
must be zero. All CIA registers are
accessed with longword granularity. For more specific details on the CIA CSRs, refer to the
Digital Semiconductor 21172 Core Logic Chipset Technical Reference Manual
.
Table A–8 Hardware-Specific Register Address Space
addr<39:28> Selected Region addr<27:6> addr<5:0>
1000.0111.0100
1
CIA control,
diagnostic, error
registers
LW address 000000
1000.0111.0101
1
CIA memory control
registers
LW address 000000
1000.0111.0110
1
CIA PCI address
translation (S/G,
windows, and so on)
LW address 000000
1000.0111.0111 to
1000.0111.1111
Reserved —
—