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Digital Equipment Corporation

Maynard, Massachusetts

Digital Semiconductor

AlphaPC 164 Motherboard

Technical Reference Manual

Order Number: EC–QPFYB–TE

Revision/Update Information:

This manual supersedes the Digital Semiconductor

AlphaPC 164 Motherboard Technical Reference

Manual (EC–QPFYA–TE).

Preliminary

Summary of content (164 pages)

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Digital Semiconductor AlphaPC 164 Motherboard Technical Reference Manual Order Number: EC–QPFYB–TE Revision/Update Information: This manual supersedes the Digital Semiconductor AlphaPC 164 Motherboard Technical Reference Manual (EC–QPFYA–TE). Preliminary Digital Equipment Corporation Maynard, Massachusetts http://www.digital.
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January 1997 Possesion, use, or copying of the software described in this publication is authorized only pursuant to a valid written licence from DIGITAL or an authorized sublicensor. While DIGITAL believes the information included in this publication is correct as of the date of publication, it is subject to change without notice.
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Contents Preface 1 xi Introduction to the AlphaPC 164 Motherboard 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 2 ........................................................... System Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Semiconductor 21172 Core Logic Chipset . . . . . . . . . . . . . . . Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L3 Bcache Subsystem Overview . . . . . . . .
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3 Power and Environmental Requirements 3.1 3.2 3.3 4 AlphaPC 164 Bcache Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Semiconductor 21172 Core Logic Chipset . . . . . . . . . . . . . . . . . . CIA Chip Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSW Chip Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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A System Address Mapping A.1 A.2 A.2.1 A.2.2 A.3 A.3.1 A.3.2 A.3.3 A.3.4 A.3.4.1 A.3.4.2 A.3.4.3 A.3.5 A.4 A.4.1 A.4.1.1 A.4.1.2 A.4.2 A.4.3 A.4.3.1 A.4.4 A.4.4.1 A.4.4.2 B Address Mapping Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 21164 Address Space Configuration Supported by the CIA . . . . . . . A–2 21164 Access to Address Space . . . . . . . . . . . . . . . . . . . . . . . . A–4 PCI Access to Address Space . . . . . . . . . . . . . . . . . . . . . . . . . .
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B.4.1 B.5 B.6 B.6.1 B.6.2 B.6.3 B.7 C SIO PCI-to-ISA Bridge Configuration Address Space . . . . . . . . . . . . PCI Special/Interrupt Acknowledge Cycle Address Space . . . . . . . . . . . . Hardware-Specific and Miscellaneous Register Space . . . . . . . . . . . . . . CIA Main CSR Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CIA Memory Control CSR Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . CIA PCI Address Translation Map Space . . . . . . . . . . . . .
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Figures 1–1 1–2 2–1 2–2 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 4–9 4–10 5–1 A–1 A–2 A–3 A–4 A–5 A–6 A–7 A–8 A–9 A–10 A–11 A–12 A–13 A–14 A–15 A–16 A–17 A–18 A–19 A–20 A–21 A–22 C–1 AlphaPC 164 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . Division of Flash Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AlphaPC 164 Jumper/Connector/Component Location. . . . . . . . . . . . . . AlphaPC 164 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . .
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Tables 1–1 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 2–12 2–13 2–14 2–15 2–16 2–17 2–18 3–1 4–1 4–2 5–1 5–2 A–1 A–2 A–3 A–4 A–5 A–6 A–7 A–8 A–9 A–10 A–11 A–12 A–13 B–1 B–2 B–3 B–4 viii Main Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AlphaPC 164 Jumper/Connector/Component List. . . . . . . . . . . . . . . . . . Peripheral Component Interface (PCI) Bus Connector Pinouts. . . . . . . . ISA Expansion Bus Connector Pinouts (J33, J35) . . . . . . . . . . .
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B–5 B–6 B–7 B–8 B–9 B–10 B–11 B–12 B–13 B–14 C–1 C–2 SIO Bridge Operating Register Address Space Map. . . . . . . . . . . . . . . . Flash ROM Memory Addresses (Within Segment) . . . . . . . . . . . . . . . . . Map of Flash ROM Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash ROM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Bits and PCI Device IDSEL Pins . . . . . . . . . . . . . . . . . . . . . . . .
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Preface Overview This manual describes the DIGITAL AlphaPC 164 motherboard, a module for computing systems based on the Digital Semiconductor 21164 Alpha microprocessor and the Digital Semiconductor 21172 core logic chipset. Audience This manual is intended for system designers and others who use the AlphaPC 164 motherboard to design or evaluate computer systems based on the Digital Semiconductor 21164 Alpha microprocessor and the Digital Semiconductor 21172 core logic chipset.
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• Chapter 4, Functional Description, provides a functional description of the AlphaPC 164 motherboard, including the 21172 core logic chipset, L3 backup cache (Bcache) and memory subsystems, system interrupts, clock and power subsystems, and peripheral component interconnect (PCI) and Industry Standard Architecture (ISA) devices. • Chapter 5, Upgrading the AlphaPC 164, describes how to upgrade the AlphaPC 164 motherboard’s DRAM memory and microprocessor speed.
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Bit/Field Abbreviation Description RO (read only) RW (read/write) WO (write only) • Bits and fields specified as RO can be read but not written. Bits and fields specified as RW can be read and written. Bits and fields specified as WO can be written but not read. Binary Multiples The abbreviations K, M, and G (kilo, mega, and giga) represent binary multiples and have the following values.
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Data Units The following data-unit terminology is used throughout this manual. Term Words Bytes Bits Other Byte Word Longword/Dword Quadword Octaword Hexword ½ 1 2 4 8 16 1 2 4 8 16 32 8 16 32 64 128 256 — — Longword 2 Longwords 2 Quadwords 2 Octawords Note Notes emphasize particularly important information. Numbering All numbers are decimal or hexadecimal unless otherwise indicated. The prefix 0x indicates a hexadecimal number.
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In some cases, more than one schematic page is referenced. For example, the following specifies schematic pages 10 through 13: “. . . the data switches (pc164.10–13) . . .” Signal Names All signal names are printed in boldface type. Signals whose name originates in an industry-standard specification, such as PCI or IDE, are printed in the case as found in the specification (usually uppercase). Active-high signals are indicated by the _h suffix.
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Operations that produce UNPREDICTABLE results might also produce exceptions. – An occurrence specified as UNPREDICTABLE may or may not happen based on an arbitrary choice function. The choice function is subject to the same constraints as are UNPREDICTABLE results and must not constitute a security hole. Specifically, UNPREDICTABLE results must not depend upon, or be a function of, the contents of memory locations or registers that are inaccessible to the current process in the current access mode.
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1 Introduction to the AlphaPC 164 Motherboard This chapter provides an overview of the AlphaPC 164 motherboard, its components, features, and uses. The Digital Semiconductor AlphaPC 164 Motherboard (AlphaPC 164) is a module for computing systems based on the Digital Semiconductor 21172 core logic chipset. The AlphaPC 164 provides a single-board hardware and software development platform for the design, integration, and analysis of supporting logic and subsystems.
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System Components and Features Figure 1–1 AlphaPC 164 Functional Block Diagram Index 19 Control 21164 Alpha Microprocessor 1MB L3 Bcache Bcache Tag 10 Data 128 Check DECchip 21172 Core Logic Chipset DECchip 21172-BA Data Switch 16 (X4) 37 DRAM SIMM Sockets (X8) Data 64 Control Address 128/256-Bit Data DECchip 21172-CA Control, I/O Interface, and Address Commands Address/Control PCI Bus IDE Controller Support - Oscillator - Serial ROM 2 Dedicated 64-Bit PCI Slots 2 Dedicated 32-Bit PCI
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System Components and Features 1.1.1 Digital Semiconductor 21172 Core Logic Chipset The 21164 microprocessor is supported by the 21172 core logic chipset. The chipset consists of the following two application-specific integrated circuit (ASIC) types: • One copy of the Digital Semiconductor 21172-CA control, I/O interface, and address (CIA) chip provides the interface between the 21164 microprocessor, main memory (addressing and control), and the PCI bus.
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System Components and Features Table 1–1 Main Memory Sizes Total Memory 128-Bit Data Bus Width with 4 SIMMs of Size... 16MB 32MB 64MB 128MB 256MB 1Mb X 36 2Mb X 36 4Mb X 36 8Mb X 36 16Mb X 36 Total Memory 256-Bit Data Bus Width with 8 SIMMs of Size... 32MB 64MB 128MB 256MB 512MB 1Mb X 36 2Mb X 36 4Mb X 36 8Mb X 36 16Mb X 36 1.1.3 L3 Bcache Subsystem Overview The AlphaPC 164 board-level L3 backup cache (Bcache) is a 1MB, direct-mapped, synchronous SRAM with a 128-bit data path.
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System Components and Features 1.1.5 ISA Interface Overview The ISA bus provides the following system support functions: • Two expansion slots. • An SMC FDC37C935 combination controller chip provides: • – A mouse and keyboard controller – A diskette controller – Two universal asynchronous receiver-transmitters (UARTs) with full modem control – A bidirectional parallel port – A time-of-year (TOY) clock Operating system support—provided by a 1MB flash ROM that contains supporting firmware.
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Flash Memory Organization 1.2 Flash Memory Organization The AlphaPC 164 incorporates a 1MB flash having sixteen 64KB blocks or segments. Figure 1–2 shows the division of these blocks. The first 64KB block, block 0, contains the fail-safe booter. The next fourteen 64KB blocks, blocks 1 through 14 (896KB), are allocated to the primary firmware. The last block, block 15, is allocated for storing any environment variables that the primary firmware needs to save.
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Fail-Safe Booter 1.3 Fail-Safe Booter The fail-safe booter is a small (64KB) firmware program that provides a recovery procedure when the flash is corrupted. When the flash becomes corrupted, this utility can be run to facilitate booting a firmware update utility from a floppy diskette that is capable of reprogramming the flash. When the fail-safe booter runs, it expects to find a floppy containing the file fwupdate.exe. If the file is found, the fail-safe booter loads and executes this program.
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Software Support 1.4.2 Alpha SRM Console Firmware The Alpha SRM Console firmware is required to install and boot DIGITAL UNIX on the AlphaPC 164. This Digital Semiconductor firmware comes factory installed in the 21A04-B2 variation of the AlphaPC 164. When installed, this firmware occupies the flash blocks reserved for the primary firmware. Binary images of the Alpha SRM Console firmware are included on the EBSDK compact disk, along with a license describing the terms for use and distribution. 1.4.
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2 System Configuration and Connectors This chapter describes the user-environment configuration, board connectors and functions, and jumper functions. It also identifies jumper and connector locations. The AlphaPC 164 uses jumpers to implement configuration parameters such as system speed, data path width, and boot parameters. These jumpers must be configured for the user’s environment. Onboard connectors are provided for the I/O interfaces, SIMMs, and serial and parallel peripheral ports.
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Figure 2–1 AlphaPC 164 Jumper/Connector/Component Location J30 J35 J31 J33 U52 U51 2 26 1 25 J32 1 3 J28 U49 U48 U50 J29 J27 B1 J25 J21 1 3 1 1 3 1 5 4 U34 J20 U41 U39 J22 J26 1 2 U40 U35 J19 U36 J23 J18 33 1 2 34 J24 U25 U29 U21 U22 J13 1 2 1 2 J14 U15 U16 U17 U10 U11 U12 J16 U18 39 40 39 40 J15 U14 U5 U6 U7 Top: Mouse Bottom: Keyboard J4 Cache SRAM (L3) Top: COM1 Bottom: COM2 U2 1 3 20 J3 2–2 10 View from edge 11 1 J1 J5 J6 System Configu
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Table 2–1 AlphaPC 164 Jumper/Connector/Component List Item Number Description Item Number Description B1 J2 J4 J6 J8 J10 J12 J14 J16 J19 J21 RTC battery (CR2032) Fan power, enclosure (+12V) COM1/COM2 (DB9) connectors DRAM SIMM 1 [71:36] connector DRAM SIMM 3 [143:108] connector DRAM SIMM 5 [215:180] connector DRAM SIMM 7 [287:252] connector IDE drive 0/1 connector Parallel I/O connector PCI slot 3 (32-bit) Microprocessor fan/fan sense connector Speaker connector Halt button connector Power LED connector
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AlphaPC 164 Jumper Configurations 2.1 AlphaPC 164 Jumper Configurations The AlphaPC 164 has three groups of jumpers at location J1, J30, and J31. These jumpers set the hardware configuration and boot options. Figure 2–1 shows the jumper location on the AlphaPC 164. Figure 2–2 shows the jumper functions for each group. Section 2.1.1 through Section 2.1.7 describe the jumper configurations.
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AlphaPC 164 Jumper Configurations Figure 2–2 AlphaPC 164 Configuration Jumpers J30 System Configuration Jumpers IRQ3 1 IRQ2 3 IRQ1 5 IRQ0 7 CF0 9 CF1 11 CF2 13 CF3 15 CF4 17 CF5 19 CF6 21 Mini-Debugger (Default Out) CF7 23 Boot_Option (Default Out) 25 Not Used Frequency 366 MHz 400 MHz 433 MHz 466 MHz 500 MHz Ratio 11 12 13 14 15 IRQ3 IRQ2 IRQ1 IRQ0 In Out Out Out Out In In Out Out In Out Out Out Out Out In Out Out Out Out All other combinations Comments Reserved Reserved (
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AlphaPC 164 Jumper Configurations 2.1.2 System Clock Divisor Jumpers (IRQ3 through IRQ0) The system clock divisor jumpers are located at J30—1/2 (IRQ3), J30—3/4 (IRQ2), J30—5/6 (IRQ1), and J30—7/8 (IRQ0). The jumper configuration set in IRQ3 through IRQ0 determines the frequency of the microprocessor’s system clock output. These four jumpers set the speed at power-up as listed in Figure 2–2. The microprocessor frequency divided by the ratio determines the system clock frequency. 2.1.
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AlphaPC 164 Connector Pinouts 2.1.7 Flash ROM Update Jumper (J31) When J31—2/3 are jumpered together (default), the flash ROM is write-enabled. When J31—1/2 are jumpered together, the flash ROM is write-protected. 2.2 AlphaPC 164 Connector Pinouts This section lists the pinouts of all connectors (see Table 2–2 through Table 2–18). See Figure 2–1 for connector locations.
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AlphaPC 164 Connector Pinouts Table 2–2 (Continued) Peripheral Component Interface (PCI) Bus Connector Pinouts Pin Signal Pin Signal Pin Signal Pin Signal B43 B47 B51 B55 B59 +3V AD[12] Not used AD[05] +5V B44 B48 B52 B56 B60 C/BE#[1] AD[10] AD[08] AD[03] ACK64# B45 B49 B53 B57 B61 AD[14] GND AD[07] GND +5V B46 B50 B54 B58 B62 GND Not used +3V AD[01] +5V 64-Bit PCI Connectors Only (J26, J29) A63 A67 A71 A75 A79 A83 A87 A91 B63 B67 B71 GND PAR64 D[58] +5V D[48] D[42] GND D[32] — GND D[59]
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AlphaPC 164 Connector Pinouts Table 2–3 (Continued) ISA Expansion Bus Connector Pinouts (J33, J35) Pin Signal Pin Signal Pin Signal Pin Signal 49 53 57 61 65 69 IRQ3 TC +5V GND IOCS16# IRQ11 50 54 58 62 66 70 SA6 SA4 SA2 SA0 LA23 LA21 51 55 59 63 67 71 DACK2# BALE OSC MEMCS16# IRQ10 IRQ12 52 56 60 64 68 72 SA5 SA3 SA1 SBHE# LA22 LA20 73 77 81 85 89 93 97 IRQ15 DACK0# DACK5# DACK6# DACK7# +5V GND 74 78 82 86 90 94 98 LA19 LA17 MEMW# SD9 SD11 SD13 SD15 75 79 83 87 91 95 — IRQ14 DRQ0 DRQ5
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AlphaPC 164 Connector Pinouts Table 2–5 IDE Drive Bus Connector Pinouts (J13, J14) Pin Signal Pin Signal Pin Signal Pin Signal 1 5 9 13 17 21 25 29 RESET IDE_D6 IDE_D4 IDE_D2 IDE_D0 MARQ IOR MACK 2 6 10 14 18 22 26 30 GND IDE_D9 IDE_D11 IDE_D13 IDE_D15 GND GND GND 3 7 11 15 19 23 27 31 IDE_D7 IDE_D5 IDE_D3 IDE_D1 GND IOW CHRDY IRQ 4 8 12 16 20 24 28 32 IDE_D8 IDE_D10 IDE_D12 IDE_D14 NC (key pin) GND BALE IOCS16 33 37 ADDR1 CS0 34 38 NC CS1 35 39 ADDR0 ACT 36 40 ADDR2 GND Table 2–6 D
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AlphaPC 164 Connector Pinouts Table 2–8 COM1/COM2 Serial Line Connector Pinouts (J4) COM1 Pin (Top) COM1 Signal COM2 Pin (Bottom) COM2 Signal 1 2 3 4 5 6 7 8 9 DCD1 RxD1 TxD1 DTR1 SG1 DSR1 RTS1 CTS1 RI1 1 2 3 4 5 6 7 8 9 DCD2 RxD2 TxD2 DTR2 SG2 DSR2 RTS2 CTS2 RI2 Table 2–9 Keyboard/Mouse Connector Pinouts (J15) Keyboard Pin (Top) Keyboard Signal Mouse Pin (Bottom) Mouse Signal 1 2 3 4 5 6 1 2 3 4 5 6 MSDATA NC GND +5V MSCLK NC KBDATA NC GND +5V KBCLK NC Table 2–10 SROM Test Data Input Connec
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AlphaPC 164 Connector Pinouts Table 2–11 Input Power Connector Pinouts (J3) Pin Voltage Pin Voltage Pin Voltage Pin Voltage 1 5 9 13 17 +3.3 V dc Ground NC Ground Ground 2 6 10 14 18 +3.3 V dc +5 V dc +12 V dc NC –5 V dc 3 7 11 15 19 Ground Ground +3.
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AlphaPC 164 Connector Pinouts Table 2–15 Power LED Connector Pinouts (J27) Pin Signal Name 1 2 3 4 5 POWER_LED_L GND NC NC NC Pull-up to +5V — — — — Table 2–16 IDE Drive LED Connector Pinouts (J28) Pin Signal Name 1 2 HD_ACT_L HD_LED_L Hard drive active Pull-up to +5V Table 2–17 Reset Button Connector Pinouts (J24) Pin Signal Name 1 2 RESET_BUTTON GND Reset system — Table 2–18 Halt Button Connector Pinouts (J25) Pin Signal Name 1 2 HALT_BUTTON GND Halt system — Note: The Halt butto
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3 Power and Environmental Requirements This chapter describes the AlphaPC 164 power and environmental requirements, and physical board parameters. 3.1 Power Requirements The AlphaPC 164 derives its main dc power from a user-supplied power supply. The board has a total power dissipation of 116 W, excluding any plug-in PCI and ISA devices. An onboard +5 V to +2.5 V dc-to-dc convertor is designed to handle 15 A of current. Table 3–1 lists the power requirement for each dc supply voltage.
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Environmental Requirements 3.2 Environmental Requirements The 21164 microprocessor is cooled by a small fan blowing directly into the chip’s heat sink. The AlphaPC 164 is designed to run efficiently using only this fan. Additional fans may be necessary depending upon cabinetry and I/O board requirements. Such fans (12 V dc) may be connected to J2 and J22.
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4 Functional Description This chapter describes the functional operation of the AlphaPC 164. The description introduces the Digital Semiconductor 21172 core logic chipset and describes its implementation with the 21164 microprocessor, its supporting memory, and I/O devices. Figure 1–1 shows the AlphaPC 164 major functional components. Information, such as bus timing and protocol, found in other data sheets and reference documentation is not duplicated.
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AlphaPC 164 Bcache Interface 4.1 AlphaPC 164 Bcache Interface The 21164 microprocessor controls the board-level L3 backup cache (Bcache) array (see Figure 4–1). The data bus (data_h<127:0>), check bus (data_check_h<15:0>), tag_dirty_h, and tag_ctl_par_h signals are shared with the system interface.
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Digital Semiconductor 21172 Core Logic Chipset 4.2 Digital Semiconductor 21172 Core Logic Chipset The 21172 core logic chipset provides a cost-competitive solution for designers using the 21164 microprocessor to develop uniprocessor systems.
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4–4 Functional Description pc164.2 21164 128bit_l * addr_bus_req adr_cmd_par cack cmd<3:0> dack fill fill_error fill_id idle_bc int4_valid<3:0> sys_res<1:0> tag_ctl_par tag_dirty victim_pending System Control* addr_h<39:4> J1 data_check_h<15:0> data_h<127:0> 64-Bit PCI I/O Bus and Address mem_dat<287:144> mem_dat<143:0> pc164.7 memrasa_l<7:0> memrasb_l<7:0> memcas_l<7:0> memwe_l memadr<11:0> iod<63:0> iod_ecc<7:0> Control, I/O Interface, cmc<8:0> ioc<<6:0> mem_en pc164.8-.
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Digital Semiconductor 21172 Core Logic Chipset 4.2.1 CIA Chip Overview The CIA application-specific integrated circuit (ASIC) accepts addresses and commands from the 21164 microprocessor and drives the main memory array with the address and control signals. It also provides an interface to the 64-bit PCI I/O bus. The CIA chip provides the following functions: • Serves as the interface between the 21164 microprocessor, main memory (addressing and control), and the PCI bus.
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PCI Devices The DSW chip contains the memory interface data path. This includes a 64-byte victim buffer, a 32-byte I/O read buffer, four 32-byte I/O write buffers, and two DMA buffers. The four DSW chips receive data from the CPU by means of the 128-bit CPU data bus. They transfer data to and from the CIA by means of the 64-bit IOD bus. Any data directed to or from the PCI bus must be transferred through the CIA. The DSW chips provide the system with a selectable 128-bit or 256-bit-wide memory path.
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PCI Devices Figure 4–3 AlphaPC 164 PCI Bus Devices CIA pc164.7 PCI Bus 82378ZB SIO Bridge PCI0646 IDE Controller pc164.22 pc164.18 ISA Bus Drive 0 Drive 1 J14 J13 Device IDSEL Select pci_ad16 Slot 2 pci_ad17 Slot 0 Slot 1 pci_ad18 SIO Bridge pci_ad19 Slot 3 pci_ad20 pci_ad21 Reserved IDE Control pci_ad22 PCI Slot 0 J29 PCI Slot 1 J26 PCI Slot 2 J20 PCI Slot 3 J19 PC164-04 The PCI bus supports multiplexed, burst mode, read and write transfers.
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PCI Devices The bridge from the 21164 system bus to the 64-bit PCI bus is provided by the CIA chip. It generates the required 32-bit PCI address for 21164 I/O accesses directed to the PCI. It also accepts 64-bit double address cycles and 32-bit single address cycles. However, the 64-bit address support is subject to some constraints. Refer to Appendix A for more information on these constraints. 4.3.1 Saturn-IO (SIO) Chip The 82378ZB SIO chip provides the bridge between the PCI bus and the ISA bus.
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ISA Bus Devices 4.4 ISA Bus Devices Figure 4–4 shows the AlphaPC 164 ISA bus implementation with peripheral devices and connectors. Two dedicated ISA expansion slots are provided. System support features such as serial lines, parallel port, diskette controller, keyboard/mouse control, and time-of-year clock are embedded on the module by means of an FDC37C935 combination controller chip. Also shown is the utility bus (Ubus) with its system support devices. 4.4.
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4–10 Functional Description pc164.22 PCI-to-ISA Bridge 82378ZB PCI Bus sa<15:0> pc164.25 K/M sa<2:0> ecasaddr<2> ior,iow ubus_data<0> J15 COM1/2 J4 Parallel J16 Diskette J18 pc164.4 Transceivers sa<19:0> Combination Controller 37C935 sd<7:0> ubus_data<7:0> pc164.17 Ubus Decoder pc164.4 Config. Jumpers sd<15:0> la<23:17> adr19 sa<18:0> pc164.28 Flash ROM 1M X 8b pc164.23 J33 PC164-05 J35 ISA1 pc164.
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Interrupts 4.4.2 Utility Bus Memory Device The AlphaPC 164 Ubus drives a flash ROM memory device. The flash ROM chip provides 1MB of flash memory for operating system support. Flash data is accessed through 20 address inputs. The low-order 19 address bits are driven by ISA bus sa<18:0>. The high-order 20th bit (flash_adr19) is driven by the Ubus decode PLA. Address bit flash_adr19 can be changed by writing to ISA I/O port x800.
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4–12 Functional Description pc164.23 ISA Slots pc164.18 irq<15:3 ,1> <3:0> pc164.25 Combination Controller sio_int pci_isa_irq Ubus<7:0> pc164.17 System Interrupt PLD <15:9,7:3,1> drq<7:5, 3:0> ide_int_l pci_int xn _l IDE Controller pc164.20-.21 PCI Slots PCI Bus pc164.22 PCI-to-ISA Bridge pc164.7 Control, I/O Interface, and Address sio_nmi cia_error pc164.
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Interrupts Table 4–1 AlphaPC 164 System Interrupts 21164 Interrupt IPL1 Suggested Usage AlphaPC 164 Usage cpu_irq<0> 20 Corrected system error Corrected ECC error and sparse space reserved encodings detected by CIA cpu_irq<1> 21 — PCI and ISA interrupts cpu_irq<2> 22 Interprocessor and timer interrupts TOY clock interrupt cpu_irq<3> 23 — Reserved pwr_fail_irq 30 Powerfail interrupt Reserved sys_mch_chk_irq 31 System machine check interrupt SIO NMI and CIA errors mch_hlt_irq Halt
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Interrupts Table 4–2 ISA Interrupts Interrupt Number Interrupt Source IRQ0 Internal timer IRQ1 Keyboard IRQ2 Interrupt from controller 2 IRQ3 COM2 IRQ4 COM1 IRQ5 Available IRQ6 Diskette IRQ7 IRQ8# Reserved IRQ9 Available IRQ10 Available IRQ11 Available IRQ12 Mouse IRQ13 Available IRQ14 IDE IRQ15 IDE 1 4–14 Parallel port 1 The # symbol indicates an active low signal.
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Interrupts 4.5.1 Interrupt PLD Function The MACH210A PLD is an 8-bit I/O slave on the ISA bus at hex addresses 804, 805, and 806. This is accomplished by a decode of the three ISA address bits sa<2:0> and the three ecas_addr<2:0> bits. Each interrupt can be individually masked by setting the appropriate bit in the mask register (see Figure 4–6). An interrupt is disabled by writing a 1 to the desired position in the mask register. An interrupt is enabled by writing a 0.
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System Clocks 4.6 System Clocks Figure 4–7 shows the AlphaPC 164 clock generation and distribution scheme. The AlphaPC 164 system includes input clocks to the microprocessor as well as clock distribution for the various system memory and I/O devices. There are other miscellaneous clocks for ISA bus support. System clocking can be divided into the following three main areas: • Microprocessor input clock — The input clock runs at the operating frequency of the 21164 microprocessor.
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System Clocks Figure 4–7 AlphaPC 164 System Clocks Socketed Oscillator 36.6-MHz (Default) pc164.3 Socketed PLL Clock Generator X10 clk_in_h 21164 Microprocessor clk_in_l pc164.3 irq_h<3:0> J30 Jumpers pc164.2 sys_clk_out1 PLL Clock Driver cia_clk_h CIA DSW0 DSW1 dsw0_clk_h dsw1_clk_h DSW2 dsw2_clk_h DSW3 dsw3_clk_h pciclk_slot0 pciclk_slot1 pciclk_slot2 PCI Slots pc164.20,21 pciclk_slot3 pciclk_ide pciclk_arb pciclk_sio 82378ZB pc164.4 Bridge 14.
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System Clocks At system reset, the 21164 microprocessor’s irq_h<3:0> pins are driven by the clock divisor values set by four jumpers on J30. During normal operation, these signals are used for interrupt requests. The pins are either switched to ground or pulled up in a specific combination to set the 21164 microprocessor’s internal divider. The divisor is programmable and can range from 3 to 15. (Refer to Section 2.1.2 for a list of jumper combinations.
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Reset and Initialization 4.7 Reset and Initialization A TL7702B power monitor senses the +3.3-V rail to ensure that it is stable before +2.5 V is applied to the 21164 microprocessor. In normal operation, should the +3.3-V rail fall below 2.5 V, the power monitor enables shdn_l, which turns off the +2.5-V regulator (pc164.32). An external reset switch can be connected to J24 (pc164.28). The reset function initializes the 21164 microprocessor and the system logic.
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4–20 Functional Description Power Supply Reset Switch Fan Sensor +3 V J3 J24 8 pc164.31 J3 2 1 pc164.28 2 pc164.28 J21 pc164.31 p_dcok Debounce fan_ok_l pc164.32 Power Sense shdn_l pc164.30 b_dcok To +2.5-V Regulator pc164.30 rst_l pc164.29 dc_ok_h sys_reset_l Buffering sys_reset(n)_l irq_reset_l pc164.22 SIO PC164-08 pc164.2 21164 IRQ Mux System Reset pc164.
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Serial ROM 4.8 Serial ROM The serial ROM (SROM) provides the following functions: • Initializes the CPU’s internal processor registers (IPRs). • Sets up the microprocessor’s internal L1/L2 caches. • Performs the minimum I/O subsystem initialization necessary to access the real-time clock (RTC) and the system’s flash ROM. • Detects CPU speed by polling the periodic interrupt flag (PIF) in the RTC. • Sets up memory and backup cache (Bcache) parameters based on the speed of the CPU.
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DC Power Distribution Figure 4–9 Serial ROM srom_dat_h 21164 srom_oe_l SROM real_srom_d MUX srom_clk_h pc164.2 2 5 pc164.3 pc164.3 srom_clk_l test_srom_d test_srom_d_l J32 pc164.26 eb164.3 PC164-09 4.9 DC Power Distribution The AlphaPC 164 derives its system power from a user-supplied PC power supply. The power supply must provide +12 V dc and -12 V dc, -5 V dc, +3 V dc, and +5 V dc (Vdd). The dc power is supplied through power connector J3 (pc164.31). (See Figure 4–10.
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10 17 January 1997 – Subject to Change 1,2,11 3,5,7,13 15,16,17 18 4,6,19,20 12 pc164.31 +3.3 V +3.3-V Pull-Ups GND (Vss) -5 V pc164.23 ISA Conn. +12 V -12 V +5 V (Vdd) Power Connector J3 pc164.21 PCI64 Conn. pc164.20 PCI32 Conn. Spkr vddi_level_h Pull-Downs +5-V Pull-Ups pc164.32 +2.5-V Regulator +2.5 V (Vddi) Integrated Circuits/Clocks pc164.28 Flash Fan PC164-10 pc164.
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System Software 4.10 System Software AlphaPC 164 software consists of the following: • Serial ROM code • Mini-Debugger code • Windows NT ARC firmware • Operating systems The serial ROM code, Mini-Debugger code, and Windows NT ARC firmware are all included with the AlphaPC 164 and do not require a license. Only binaries for the Windows NT ARC firmware are included, not the sources. Operating systems are available as licensed products. Refer to Appendix F for a list of related documentation. 4.10.
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System Software The Mini-Debugger provides the following: • Basic hardware debugging capability • The capability to load code through the SROM test port • A monitor that can point to hardware addresses, and exercise registers and devices at those locations • The ability to examine and deposit memory locations • A case-independent command language • Support for variable CPU speeds and communication baud rates For additional information, refer to the Alpha Microprocessors SROM MiniDebugger User’
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5 Upgrading the AlphaPC 164 The AlphaPC 164 can be upgraded in two ways. For higher system speed or greater throughput, DRAM memory can be upgraded either by replacing SIMMs with those of greater size, or by widening the memory bus from 128 bits to 256 bits by adding more SIMMs. For higher CPU speed, the Digital Semiconductor 21164 microprocessor can be replaced with a higher speed Alpha chip. The following sections describe the upgrade processes.
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Upgrading DRAM Memory Table 5–1 AlphaPC 164 DRAM Memory Configurations Total Memory 128-Bit Memory Mode (J1 In) J5 Through J8 Populated with SIMM Sizes... 16MB 32MB 64MB 128MB 256MB 1Mb X 36 2Mb X 36 4Mb X 36 8Mb X 36 16Mb X 36 Total Memory 256-Bit Memory Mode (J1 Out) J5 Through J12 Populated with SIMM Sizes... 32MB 64MB 128MB 256MB 512MB 1Mb X 36 2Mb X 36 4Mb X 36 8Mb X 36 16Mb X 36 5.2 Upgrading DRAM Memory There are three options for upgrading DRAM memory (see Table 5–2).
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Increasing Microprocessor Speed To widen the memory bus to its 256-bit maximum (upgrade option 2), add four SIMMs and make a jumper change (remove J1). The SIMMs that you add must be of the same size (nMb X 36-bit) and have an access time equal to or less than the four SIMMs already in the system. Refer to Figure 2–1 for SIMM connector and jumper location. To upgrade DRAM memory, perform the following steps: 1. Observe antistatic precautions. Handle SIMMs only at the edges to prevent damage. 2.
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Increasing Microprocessor Speed When replacing the microprocessor chip, the thermal conducting GRAFOIL pad should be replaced with it. A parts kit, including the heat sink, GRAFOIL pad, two hex nuts, heat sink clips, 60-mm fan, fan guard, and four screws is available from: United Machine and Tool Design River Road Fremont NH 03044 Phone: 603.642.5040 FAX: 603.642.5819 When replacing the microprocessor chip with one of a different speed rating, the clock oscillator must also be changed.
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Increasing Microprocessor Speed 5.3.2 Required Tools The following tools are required when replacing the microprocessor chip: A TS30 manual nut/torque driver (or equivalent) with the following attachments is required to affix the heat sink and fan to the microprocessor’s IPGA package: • 1/4-inch hex bit • 7/16-inch socket with 1/4-inch hex drive • #2 Phillips-head screwdriver bit 5.3.
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Increasing Microprocessor Speed 2. Lift the ZIF socket actuator handle to a full 90° angle. 3. Ensure that all the pins on the microprocessor package are straight. 4. The ZIF socket and microprocessor are keyed to allow for proper installation. Align the microprocessor, with its missing AD01 pin, with the corresponding plugged AD01 position on the ZIF socket. Gently lower into position. 5. Close the ZIF socket actuator handle to its locked position. 6.
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Increasing Microprocessor Speed a. Put the GRAFOIL thermal pad in place. The GRAFOIL pad is used to improve the thermal conductivity between the chip package and the heat sink by replacing micro air pockets with a less insulative material. Perform the following steps to position the GRAFOIL pad: 1. Perform a visual inspection of the package slug to ensure that it is free of contamination. 2. Wearing clean gloves, pick up the GRAFOIL pad.
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Increasing Microprocessor Speed 3. Secure the fan and fan guard to the heat sink with four 6–32 X 0.875-inch screws. 4. Plug the fan power/sensor cable into connector J21 (see Figure 2–1). Note: 5–8 When installing a 400-MHz, 433-MHz, 466-MHz, or 500-MHz microprocessor, you must reconfigure the clock divisor jumpers on header J30 as shown in Figure 2–2. You must also change the clock oscillator at location U34. The clock oscillators and oscillator kit are available from the sources listed in Appendix D.
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A System Address Mapping This appendix describes the AlphaPC 164 motherboard’s CIA chip mapping of 40-bit 21164 physical addresses to memory addresses and I/O space addresses. It also describes translation of a 21164-initiated address into a PCI address and translation of a PCI-initiated address into a physical memory address. Topics include dense and sparse address space1, PCI addressing, scatter-gather address translation for DMA operations, and Industry Standard Architecture (ISA) requirements. A.
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21164 Address Space Configuration Supported by the CIA Figure A–1 21164 Address Space 00.0000.0000 Cached Memory 01.FFFF.FFFF 02.0000.0000 Reserved 7F.FFFF.FFFF 80.0000.0000 Noncacheable Address Space 8B.FFFF.FFFF LJ04259A.AI5 A.2 21164 Address Space Configuration Supported by the CIA As shown in Figure A–2, the CIA supports only the first 8GB of cacheable memory space; the remainder is reserved. The cacheable memory space block size is fixed at 64 bytes.
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21164 Address Space Configuration Supported by the CIA Figure A–2 21164 Address Space Configuration 39 38 37 36 35 34 33 32 31 30 Size 00 Physical Address 0 000XX 00.0000.0000 8GB Cached Memory 01.FFFF.FFFF 02.0000.0000 Reserved 0=Cached Memory Space 1=Noncached I/O Space 00XXX 7F.FFFF.FFFF 80.0000.0000 0100X 83.FFFF.FFFF 84.0000.0000 01010 84.FFFF.FFFF 85.0000.0000 01011 85.8000.0000 0110X 86.0000.
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21164 Address Space Configuration Supported by the CIA A.2.1 21164 Access to Address Space The 21164 microprocessor has access to the complete address space. It can access cached memory and CSRs, as well as all the PCI memory, I/O, and configuration regions, as shown in Figure A–3. Figure A–3 Address Space Overview 21164 Environment Main System Memory PCI Memory Space PCI Window PCI Device 21164 PCI Device PCI I/O Space CSRs PCI Configuration Space LJ-04261.AI A.2.
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21164 Address Space Configuration Supported by the CIA DMA access to system memory is achieved by means of windows through one of the following three access methods: • The direct method uses the “Monster Window” with dual address cycles where PCI address <33:0> equals memory address <33:0>. • The directly-mapped method concatenates an offset to a portion of the PCI address. • The virtually-mapped method uses a scatter-gather translation map.
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21164 Address Space Configuration Supported by the CIA The CIA generates 32-bit PCI addresses but accepts both 64-bit PCI address cycles (DAC1) and 32-bit PCI address cycles (SAC2). The following window restrictions apply to PCI main memory accesses: • Window 4, the “Monster Window,” provides full access to main memory. It is accessed by DAC cycles only with PCI address bit <40>=1. Memory address bits <33:0> equal PCI address bits <33:0>.
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21164 Address Space Configuration Supported by the CIA Figure A–5 21164 and DMA Read and Write Transactions 21164 Memory Space Cached Memory Scatter-Gather or Direct Translation PCI Windows Reserved PCI-Memory Space PCI-Memory Dense Space PCI-I/O Space PCI-Memory Sparse Space PCI-I/O Space 21164 Programmed I/O DMA Read/Write LJ04263A.
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21164 Address Space A.3 21164 Address Space This section lists and describes the 21164 address space regions. The requirements for using the address regions are also shown and described. Table A–1 lists the 21164 address regions. Table A–1 21164 Physical Address Space 21164 Address Size (GB) Selection 00.0000.0000–01.FFFF.FFFF 8 Main memory 80.0000.0000–83.FFFF.FFFF 16 PCI memory—512MB sparse space—Region 0 84.0000.0000–84.FFFF.FFFF 4 PCI memory—128MB sparse space—Region 1 85.0000.0000–85.7FFF.
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21164 Address Space The reasons for using the 21164 I/O space address map are as follows: • Provides 4GB of dense space to completely map the 32-bit PCI memory space. • Provides abundant PCI sparse memory space because sparse memory space has byte granularity and is the safest memory space to use (no prefetching). Furthermore, the larger the space, the less likely software will need to dynamically relocate the sparse space segments.
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21164 Address Space A.3.1 PCI Dense Memory Space PCI dense memory space is located in the range 86.0000.0000 to 86.FFFF.FFFF. It is typically used for memory-like data buffers such as video frame buffers or nonvolatile RAM (NVRAM). Dense space does not allow byte or word access but has the following advantages over sparse space: • Contiguous memory locations—Some software, like the default graphics routines of Windows NT, require memory-like access.
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21164 Address Space transactions. Valid longwords surrounding invalid longwords (called a “hole”) are required to be handled correctly by all PCI devices. The CIA will allow such “holes” to be issued. • Read transactions will always be performed as a burst of two or more longwords on the PCI because the minimum granularity is a quadword. The processor can request a longword but the CIA will always fetch a quadword, thus prefetching a second longword.
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21164 Address Space Address generation in dense space is described in the following list: • addr<31:5> is directly sent out on the PCI as ad<31:5>. • addr<4:2> is not sent from the 21164 microprocessor, but is inferred from int4_valid_h<3:0>. • ad<4:3> is a copy of addr<4:3>. • ad<2> differs for read and write transactions as follows: – For a read transaction, ad<2> is zero (minimum read resolution in noncached space is a quadword). – For a write transaction, ad<2> equals addr<2>. A.3.
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21164 Address Space entries in Table A–3, such as word size with address addr<6:5> = 11). The hardware will complete the reference, but the reference is not required to produce any particular result nor will the CIA report an error. • Software must use longword load or store instructions (LDL/STL) to perform a reference that is of longword length or less on the PCI bus. – The bytes to be transferred must be positioned within the longword in the correct byte lanes as indicated by the PCI byte enable.
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21164 Address Space Table A–2 int4_valid_h<3:0> and addr<4:3> for Sparse Space Write Transactions 21164 Data Cycle int4_valid_h<3:0>1 addr_h<4:3> First 0001 0010 0100 1000 00 00 01 01 Second 0001 0010 0100 1000 1100 (STQ)2 10 10 11 11 11 1 All other 2 int4_valid_h<3:0> patterns cause UNPREDICTABLE results. Only one STQ case is allowed. Table A–3 defines the low-order PCI sparse memory address bits.
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21164 Address Space Table A–3 (Continued) PCI Memory Sparse Space Read/Write Encodings Data-In Register Size Byte Offset 21164 PCI addr<4:3> addr<6:5>1 Instruction ad<2:0>2 Byte3 Enable Byte Lanes [7:0] 00 LDL, STL addr<7>,00 0000 <3:0> 11 LDQ, STQ 000 0000 <7:0> Longword 11 Quadword 11 1 Missing entries (such as word size with addr<6:5> = 112 cause 2 In PCI sparse memory space, ad<1:0> is always equal to zero. 3 UNPREDICTABLE results.
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21164 Address Space Figure A–7 PCI Memory Sparse Space Address Generation (Region 1) 21164 Address 35 34 33 39 38 0 SBZ 1 08 07 06 05 04 03 02 00 PCI QW Address int4_valid 21164 HAE_MEM CSR 31 29 28 00 43 31 29 28 Length in Bytes Byte Offset 03 02 01 00 0 0 PCI Address LJ04265A.
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21164 Address Space Figure A–9 PCI Memory Sparse Space Address Generation (Region 3) 21164 Address 35 34 33 32 31 30 39 38 1 SBZ 1 0 1 0 08 07 06 05 04 03 02 00 PCI QW Address int4_valid 21164 HAE_MEM CSR 31 08 07 02 01 00 43 31 26 25 03 02 01 00 Length in Bytes Byte Offset 0 0 PCI Address LJ-04267.AI The 21164 microprocessor provides six physical address bits <39:34> that can be used to backfill the “lost” sparse space bits.
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21164 Address Space Figure A–10 PCI Sparse I/O Space Address Translation (Region A) 21164 Address 35 34 33 32 31 30 29 39 38 1 SBZ 08 07 06 05 04 03 02 00 1 0 1 1 0 <29:8> int4_valid 21164 43 31 25 24 0 0 0 0 0 0 0 03 02 01 00 Length in Bytes Byte Offset 0 0 PCI Address LJ-04268.AI The high-order PCI address bits for region B are handled as follows: • This region has addr<34:30> equal to 101112, and addresses 32MB of PCI sparse I/O space that can be relocated.
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21164 Address Space Figure A–11 PCI Sparse I/O Space Address Translation (Region B) 21164 Address 35 34 33 32 31 30 29 39 38 1 SBZ 08 07 06 05 04 03 02 00 1 0 1 1 1 int4_valid 21164 HAE_IO CSR 31 25 24 43 31 25 24 03 02 01 00 Length in Bytes Byte Offset 0 0 PCI Address LJ04269A.AI5 The power-on self-test (POST), running POST11 software, should initialize the contents of HAE_IO and the register should then remain unchanged.
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21164 Address Space Table A–5 PCI I/O Sparse Space Read/Write Encodings PCI Data-In Register Size Byte Offset 21164 addr<4:3> addr<6:5>1 Instruction ad<2:0>1 Byte2 Enable Byte Lanes [7:0] 00 01 10 11 LDL, STL addr<7>,00 addr<7>,01 addr<7>,10 addr<7>,11 1110 1101 1011 0111 <0> <1> <2> <3> 00 01 10 LDL, STL addr<7>,00 addr<7>,01 addr<7>,10 1100 1001 0011 <1:0> <2:1> <3:2> 00 01 LDL, STL addr<7>,00 addr<7>,01 1000 0001 <2:0> <3:1> 00 LDL, STL addr<7>,00 0000 <3:0> 11 LDQ, STQ
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21164 Address Space A.3.4 PCI Configuration Space PCI configuration space is located in the address range: 87.0000.0000 to 87.1FFF.FFFF. Software designers are advised to clear CIA_CTRL[FILL_ERR_EN] when probing for PCI devices using configuration space read transactions. This will prevent the CIA from generating an ECC error if no device responds to the configuration cycle and UNPREDICTABLE data is read from the PCI bus.
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21164 Address Space Software must program CFG before running a configuration cycle. Sparse address decoding is used. Note: The CIA uses CFG<1:0> instead of unused addr<38:35> to be compatible with the Digital Semiconductor 21071 core logic chipset. The Digital Semiconductor 21071 core logic chipset is used with Alpha 21064 series microprocessors. The configuration space address is assembled as follows: • The high-order PCI address bits ad<31:24> are always zero.
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21164 Address Space .
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21164 Address Space A.3.4.1 Device Select (IDSEL) Peripherals are selected during a PCI configuration cycle if the following three statements are true: • Their IDSEL pin is asserted. • The PCI bus command indicates a configuration read or write transaction. • Address bits <1:0> are 00. Address bits <7:2> select a longword register in the peripheral’s 256-byte configuration address space. Transactions can use byte masks.
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21164 Address Space Note: If a quadword access is specified for the configuration cycle, then the least significant bit (LSB) of the register number field, ad<2>, must be zero. A quadword read/write transaction must access quadword-aligned registers. If the PCI cycle is a configuration read or write cycle, but ad<1:0> equals 012 (like a Type 1 transfer), then a device on an hierarchical bus is being selected using a PCI–PCI bridge.
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21164 Address Space • Bytes 0 and 1 contain the encoded message. • Bytes 2 and 3 contain a message-dependent (optional) data field. A read to address range 87.2000.0000 to 87.3FFF.FFFF will result in an interrupt acknowledge cycle on the PCI returning the vector data, which is provided by the PCI-to-ISA bridge, to the 21164 microprocessor. A.3.4.3 Hardware-Specific and Miscellaneous Register Space Hardware-specific and miscellaneous register space is located in the range 87.4000.0000 to 87.FFFF.FFFF.
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21164 Address Space Figure A–13 Byte/Word PCI Space PCI Memory Space - 4GB 39 38 37 36 35 34 33 32 31 1 Size 0 1 0 0 0 2 PCI Memory Address <31:2> 1 0 0 0 PCI I/O Space - 4GB 39 38 37 36 35 34 33 32 31 0 1 Size 0 1 0 0 1 PCI I/O Address PCI Type 0 Configuration Space - 4GB 39 38 37 36 35 34 33 32 31 1 Size 0 1 0 1 0 2 PCI Configuration Address <31:2> 1 0 0 0 PCI Type 1 Configuration Space - 4GB 39 38 37 36 35 34 33 32 31 1 Size 0 1 0 1 1 2 PCI Configuration Address <31:2> 1 0 0 1 MK
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21164 Address Space The size field (address bits <38:37>) is added by the 21164 hardware as shown in the following list. The software value is zero.
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PCI-to-Physical Memory Addressing A.4 PCI-to-Physical Memory Addressing This section describes direct and scatter-gather mapping through the use of windows. A.4.1 Address Mapping Windows PCI addresses coming into the CIA (32-bit or 64-bit) are mapped to the 21164 cached memory space (8GB). The CIA provides five programmable address windows that control access of PCI peripherals to system memory.
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PCI-to-Physical Memory Addressing Table A–10 PCI Target Window MASK Register (W n_MASK) W_MASK<31:20> Size of Window Value of n1 0000 0000 0000 1MB 20 0000 0000 0001 2MB 21 0000 0000 0011 4MB 22 0000 0000 0111 8MB 23 0000 0000 1111 16MB 24 0000 0001 1111 32MB 25 0000 0011 1111 64MB 26 0000 0111 1111 128MB 27 0000 1111 1111 256MB 28 0001 1111 1111 512MB 29 0011 1111 1111 1GB 30 0111 1111 1111 2GB 31 1111 1111 1111 4GB 32 All others UNPREDICTABLE – 1 Only incoming
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PCI-to-Physical Memory Addressing A.4.1.1 PCI Device Address Space A PCI device specifies the amount of memory space it requires by using base registers in its configuration space. The registers are implemented such that the address space consumed by the device is a power of two in size, and is NATURALLY ALIGNED on the size of the space consumed. A PCI device need not use all of the address range that it consumes, that is, the size of the PCI address window defined by the base address.
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PCI-to-Physical Memory Addressing Figure A–14 PCI DMA Addressing Example 21164 System PCI Device's DMA Memory Space 8KB Page Direct Map Scatter-Gather Map 21164 Memory Space (8GB) PCI Memory Space (4GB) PCI Device 0 PCI Device 1 PCI Device 2 LJ-04272.AI Figure A–14 also shows that the CIA window can be larger than the corresponding device’s DMA address range, as with device 0. Devices 1 and 2 have address ranges that are accepted by one CIA window.
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PCI-to-Physical Memory Addressing Figure A–15 PCI Target Window Compare PCI Address 63 40 Zero Detect 32 39 Compare & Hit Logic 31 n n-1 02 20 19 Hit (Window 3 Only) Target Window Hit Logic Hit Window 3 Hit Window 2 Hit Window 1 Hit Window 0 W_DAC Window Enable (WENB) 31 n n-1 Wn_BASE DAC 31 Wn_MASK 20 XXXXX n n-1 00000000 Window 3 SG Bit Window 2 SG Bit Window 1 SG Bit Window 0 SG Bit 20 11111 LJ04273A.
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PCI-to-Physical Memory Addressing A.4.2 Direct-Mapped Addressing If Wn_BASE [Wn_BASE_SG] is clear, the DMA address is direct mapped. The translated address is generated by concatenating bits from the matching window’s Tn_BASE with bits from the incoming PCI address (ad<31:0>). This process is shown in Figure A–16 with n being the LSB from the Tn_BASE column of Table A–11.
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PCI-to-Physical Memory Addressing Table A–11 Direct-Mapped PCI Target Address Translation Translated Address Source W_MASK<31:20> Window Size Tn_BASE1 PCI Address 0000 0000 0000 1MB addr<32:20> addr<19:2> 0000 0000 0001 2MB addr<32:21> addr<20:2> 0000 0000 0011 4MB addr<32:22> addr<21:2> 0000 0000 0111 8MB addr<32:23> addr<22:2> 0000 0000 1111 16MB addr<32:24> addr<23:2> 0000 0001 1111 32MB addr<32:25> addr<24:2> 0000 0011 1111 64MB addr<32:26> addr<25:2> 0000 0111 1111 128
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PCI-to-Physical Memory Addressing Each scatter-gather map entry maps an 8KB page of PCI address space into an 8KB page of 21164 address space. This offers a number of advantages to software such as: • Performance—ISA devices map to the lower 16MB of memory. The Windows NT operating system currently copies data from this part of memory to user space. The scatter-gather map avoids this copy operation. • Address management—User I/O buffers might not be physically contiguous or contained within a page.
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PCI-to-Physical Memory Addressing Table A–12 Scatter-Gather Mapped PCI Target Address Translation Scatter-Gather Map Address<33:3> W_MASK<31:20> Window Size S-G Map Table Size Tn_Base1 PCI Address 0000 0000 0000 1MB 1KB <32:10> <19:13> 0000 0000 0001 2MB 2KB <32:11> <20:13> 0000 0000 0011 4MB 4KB <32:12> <21:13> 0000 0000 0111 8MB 8KB <32:13> <22:13> 0000 0000 1111 16MB 16KB <32:14> <23:13> 0000 0001 1111 32MB 32KB <32:15> <24:13> 0000 0011 1111 64MB 64KB <32:16> <25:1
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PCI-to-Physical Memory Addressing Figure A–18 Scatter-Gather Associative TLB PCI DAC Address Cycle <31:15> 8KB CPU Page Address Hit TAG V V V V V V V V V V V V V V V V DATA V V V V V V V V V V V V V V V V PCI Address<14:13> Memory Page Address<32:13> Physical memory Dword Address PCI Address<12:2> Index LJ04276A.AI5 Each time an incoming PCI address hits in a PCI target window that has scattergather enabled, ad<31:15> are compared with the 32KB PCI page address in the TLB tag.
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PCI-to-Physical Memory Addressing Figure A–19 shows the entire translation process, from PCI address to physical address, on a window that implements scatter-gather. The MSB from the PCI address column of Table A–12 equals n-1. Both paths are indicated; the path for a TLB hit is to the right, and the path for a TLB miss is to the left. The scatter-gather TLB is shown in a slightly simplified but functionally equivalent form.
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PCI-to-Physical Memory Addressing Figure A–19 Scatter-Gather Map Translation PCI LW Address 63 40 39 32 31 20 19 n n-1 02 13 12 0000000000000000000 Offset Window Hit Compare Logic 31 W_DAC n n-1 ad_h<31:13> sent to TLB for PCI window "hit." 20 XXXXX Wn_BASE DAC indicator also sent.
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PCI-to-Physical Memory Addressing A.4.4 Suggested Use of a PCI Window Figure A–20 shows a power-up PCI window assignment (as configured by firmware) and Table A–13 lists the details. PCI window 0 was chosen for the 8MB-to-16MB ISA region because this window incorporates the mem_cs_l logic. PCI window 3 was not used as it incorporates the DAC cycle logic. PCI window 1 was chosen arbitrarily for the 1GB direct-mapped region, and PCI window 2 is not assigned.
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PCI-to-Physical Memory Addressing Table A–13 PCI Window Power-Up Configuration PCI Window Assignment Size Comments 0 Scatter-Gather 8MB Not used by firmware. mem_cs_l disabled. 1 Direct Mapped 1GB Mapped to 0GB to 1GB of main memory. 2 Disabled — — 3 Disabled — — A.4.4.1 PCA Compatibility Addressing and Holes The peripheral component architecture (PCA) allows certain ISA devices to respond to hardwired memory addresses.
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PCI-to-Physical Memory Addressing • The MAR1, 2, and 3 registers enable various BIOS regions. • The MCSCON (control) register enables the mem_cs_l decode logic, and in addition, selects a number of regions (0KB to 512KB). Figure A–21 Memory Chip Select Signal (mem_cs_l) Decode Area 4GB MCSTOM 512MB Max 16MB MCSTOH Main Memory Hole Hole MCSBOH 1MB 1MB-64KB MCSCON BIOS Area VGA Memory (A0000-BFFF) MAR1,2,3 Hole 512KB MCSCON MCSCON LJ-04279.
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PCI-to-Physical Memory Addressing Figure A–22 Memory Chip Select Signal (mem_cs_l) Logic mem_cs_l 1 PCI Address Wn_BASE Window 0 Hit Detect Logic 0 devsel Wn_MASK W0_BASE LJ-04280.AI Consequently, the window address area must be large enough to encompass the mem_cs_l region programmed into the PCI-to-ISA bridge. The remaining window attributes listed as follows are still applicable and/or required. • W0_BASE [Wn_BASE_SG] determines if scatter-gather or direct mapping is applicable.
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B I/O Space Address Maps This appendix provides lists of the physical AlphaPC 164 I/O space assignments, including CIA operating register address space maps and PCI/ISA device register maps. Refer to Appendix A for detailed information on sparse/dense space and address translation. The lists include only that portion that is unique to AlphaPC 164 and that affects or reflects the system environment.
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PCI Sparse I/O Space B.2.1.1 FDC37C935 Combination Controller Register Address Space Table B–1 lists the base address values for the SMC FDC37C935 combination diskette, serial port, parallel port, keyboard, mouse, and TOY clock controller. The general registers are located at addresses 398 (index address) and 399 (data address). For example, writing an index value of 1 to address 398 selects the function address register.
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PCI Sparse I/O Space Table B–1 (Continued) Combination Controller Register Address Space Map Address Offset Read/Write Physical Address Register 2FE 85.8000.5FC0 COM2 modem status 2FF 85.8000.5FE0 COM2 scratch pad Parallel Port Registers 3BC-R/W 85.8000.7780 Data 3BD-R 85.8000.77A0 Status 3BE-R/W 85.8000.77C0 Control 3BF-R/W 85.8000.77E0 EPP address 3C0-R/W 85.8000.7800 EPP data 0 3C1-R/W 85.8000.7820 EPP data 1 3C2-R/W 85.8000.7840 EPP data 2 3C3-R/W 85.8000.
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PCI Sparse I/O Space Table B–1 (Continued) Combination Controller Register Address Space Map Address Offset Read/Write Physical Address Register 3F8 0DLAB=1 85.8000.7F00 COM1 divisor latch (LSB) 3F9 1DLAB=0 85.8000.7F20 COM1 interrupt enable 3F9 1DLAB=1 85.8000.7F20 COM1 divisor latch (MSB) 3FA-R 85.8000.7F40 COM1 interrupt identification 3FA-W 85.8000.7F40 COM1 FIFO control 3FB 85.8000.7F60 COM1 line control 3FC 85.8000.7F80 COM1 modem control 3FD 85.8000.
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PCI Sparse I/O Space Table B–1 (Continued) Combination Controller Register Address Space Map Address Offset Read/Write Physical Address Register A 85.8000.0E00 Register A B 85.8000.0E00 Register B C 85.8000.0E00 Register C D 85.8000.0E00 Register D B.2.1.2 Flash ROM Segment Select Register The flash ROM is partitioned into two 512KB segments. The segments are selected by flash_adr19. To select the first 512KB segment, write a value of 0 to ISA port address 0x80016.
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PCI Sparse I/O Space B.2.1.4 Interrupt Control PLD Addresses Table B–4 lists the registers and memory addresses for the interrupt control programmable logic device (PLD). Table B–4 Interrupt Control PLD Addresses Offset Physical Address Register x804 85.8001.0080 Interrupt status/interrupt mask 1 x805 85.8001.00A0 Interrupt status/interrupt mask 2 x806 85.8001.00C0 Interrupt status/interrupt mask 3 B.2.
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PCI Sparse I/O Space Table B–5 (Continued) SIO Bridge Operating Register Address Space Map Offset Address Register 00D 85.C000.01A0 DMA1 master clear 00E 85.C000.01C0 DMA1 clear mask 00F 85.C000.01E0 DMA1 read/write all mask register bits 020 85.C000.0400 INT 1 control 021 85.C000.0420 INT 1 mask 040 85.C000.0800 Timer counter 1 - counter 0 count 041 85.C000.0820 Timer counter 1 - counter 1 count 042 85.C000.0840 Timer counter 1 - counter 2 count 043 85.C000.
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PCI Sparse I/O Space Table B–5 (Continued) SIO Bridge Operating Register Address Space Map B–8 Offset Address Register 08D 85.C000.11A0 DMA page register reserved 08E 85.C000.11C0 DMA page register reserved 08F 85.C000.11E0 DMA low page register refresh 090 85.C000.1200 DMA page register reserved 092 85.C000.1240 Port 92 094 85.C000.1280 DMA page register reserved 095 85.C000.12A0 DMA page register reserved 096 85.C000.12C0 DMA page register reserved 098 85.C000.
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PCI Sparse I/O Space Table B–5 (Continued) SIO Bridge Operating Register Address Space Map Offset Address Register 0D6 85.C000.1AC0 DMA2 write mode 0D8 85.C000.1B00 DMA2 clear byte pointer 0DA 85.C000.1B40 DMA2 master clear 0DC 85.C000.1B80 DMA2 clear mask 0DE 85.C000.1BC0 DMA2 read/write all mask register bits 0F0 85.C000.1E00 Coprocessor error 372 85.C000.6E40 Secondary floppy disk digital output 3F2 85.C000.7E40 Primary floppy disk digital output 40A 85.C000.
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PCI Dense Memory Space Table B–5 (Continued) SIO Bridge Operating Register Address Space Map Offset Address Register 428–42B 85.C000.8518 CH2 scatter/gather descriptor table pointer 42C–42F 85.C000.8598 CH3 scatter/gather descriptor table pointer 434–437 85.C000.8698 CH5 scatter/gather descriptor table pointer 438–43B 85.C000.8718 CH6 scatter/gather descriptor table pointer 43C–43F 85.C000.8798 CH7 scatter/gather descriptor table pointer 481 85.C000.9020 DMA CH2 high page 482 85.C000.
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PCI Dense Memory Space B.3.2 Map of Flash ROM Memory Table B–7 provides a map of flash ROM memory. Table B–7 Map of Flash ROM Memory Offset Physical Address1 Block Number2 Capacity 0.0000–0.FFFF 86.FFF8.0000–86.FFF8.FFFF 0,8 64KB 1.0000–1.FFFF 86.FFF9.0000–86.FFF9.FFFF 1,9 64KB 2.0000–2.FFFF 86.FFFA.0000–86.FFFA.FFFF 2,10 64KB 3.0000–3.FFFF 86.FFFB.0000–86.FFFB.FFFF 3,11 64KB 4.0000–4.FFFF 86.FFFC.0000–86.FFFC.FFFF 4,12 64KB 5.0000–5.FFFF 86.FFFD.0000–86.FFFD.FFFF 5,13 64KB 6.
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PCI Dense Memory Space All flash ROM accesses (except for read operations) require two bus cycles. During the first cycle, register data is written to set up the registers. During the second cycle, the read or write transaction performs the operation desired. For more information about reading, erasing, and writing the flash ROM, see the Intel Flash Memory document. Accessing the flash ROM registers requires byte access, which is only possible through use of PCI sparse memory space.
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PCI Configuration Address Space B.4 PCI Configuration Address Space The PCI configuration address space occupies physical addresses 87.0000.0000 through 87.1FFF.FFFF. The PCI configuration register set occupies this space. A read or write access to this space causes a configuration read or write cycle on the PCI. Table B–9 identifies the AlphaPC 164 PCI devices and the corresponding PCI address bit that drives the device’s idsel pin. Refer to Section A.3.
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PCI Configuration Address Space Table B–10 (Continued) SIO Bridge Configuration Address Space Map Offset Address Register 41 87.0008.0820 PCI arbiter control 42 87.0008.0840 PCI arbiter priority control 44 87.0008.0880 MEMCS# control 45 87.0008.08A0 MEMCS# bottom of hole 46 87.0008.08C0 MEMCS# top of hole 47 87.0008.08E0 MEMCS# top of memory 48 87.0008.0900 ISA address decoder control 49 87.0008.0920 ISA address decoder ROM block enable 4A 87.0008.
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PCI Special/Interrupt Acknowledge Cycle Address Space B.5 PCI Special/Interrupt Acknowledge Cycle Address Space This space occupies physical addresses 87.2000.0000 through 87.3FFF.FFFF. Refer to Section A.3.4.2 for additional information on this address space. B.6 Hardware-Specific and Miscellaneous Register Space This space occupies physical addresses 87.4000.0000 through 87.6FFF.FFFF and covers the 21172-CA (CIA) address space.
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Hardware-Specific and Miscellaneous Register Space Table B–11 (Continued) CIA Control, Diagnostic, and Error Registers Register Type Address Description Performance Monitor Registers PERF_MONITOR RO 87.4000.4000 Performance monitor register PERF_CONTROL RW 87.4000.4040 Performance control register CPU_ERR0 RO 87.4000.8000 CPU error information register 0 CPU_ERR1 RO 87.4000.8040 CPU error information register 1 CIA_ERR R/WC 87.4000.8200 CIA error register CIA_STAT RW 87.4000.
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Hardware-Specific and Miscellaneous Register Space Table B–12 (Continued) CIA Memory Control Registers Register Type Address Description MBAA RW 87.5000.0880 Memory base address register 10 MBAC RW 87.5000.0900 Memory base address register 12 MBAE RW 87.5000.0980 Memory base address register 14 TMG0 RW 87.5000.0B00 Memory timing information base register 0 TMG1 RW 87.5000.0B40 Memory timing information base register 1 TMG2 RW 87.5000.
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Hardware-Specific and Miscellaneous Register Space Table B–13 (Continued) PCI Address Translation Registers Register Type Address Description LTB_TAG0 RW 87.6000.0800 Lockable translation buffer tag0 LTB_TAG1 RW 87.6000.0840 Lockable translation buffer tag1 LTB_TAG2 RW 87.6000.0880 Lockable translation buffer tag2 LTB_TAG3 RW 87.6000.08C0 Lockable translation buffer tag3 TB_TAG0 RW 87.6000.0900 Translation buffer tag0 TB_TAG1 RW 87.6000.
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Hardware-Specific and Miscellaneous Register Space Table B–13 (Continued) PCI Address Translation Registers Register Type Address Description TB4_PAGE2 RW 87.6000.1480 Translation buffer 4 page2 TB4_PAGE3 RW 87.6000.14C0 Translation buffer 4 page3 TB5_PAGE0 RW 87.6000.1500 Translation buffer 5 page0 TB5_PAGE1 RW 87.6000.1540 Translation buffer 5 page1 TB5_PAGE2 RW 87.6000.1580 Translation buffer 5 page2 TB5_PAGE3 RW 87.6000.15C0 Translation buffer 5 page3 TB6_PAGE0 RW 87.6000.
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21164 Microprocessor Cbox IPR Space B.7 21164 Microprocessor Cbox IPR Space The 21164 microprocessor cache control and bus interface unit (Cbox) IPR space occupies physical addresses FF.FFF0.0000 through FF.FFFF.FFFF. Table B–14 lists three key 21164 registers that configure the internal L2 secondary cache (Scache) and external L3 backup cache (Bcache). For additional information, refer to the Digital Semiconductor 21164 Alpha Microprocessor Hardware Reference Manual.
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C SROM Initialization The 21164 microprocessor provides a mechanism for loading the initial instruction stream (Istream) from a compact serial ROM (SROM) to start the bootstrap procedure. The SROM executable image is limited to the size of the CPU instruction cache (Icache). Because the image is running only in the Icache, it is relatively difficult to debug.
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Firmware Interface 10. Copy the contents of the system flash ROM to memory and begin code execution. 11. Pass parameters up to the next level of firmware to provide a predictable firmware interface. C.2 Firmware Interface A firmware interface provides a mechanism for passing critical information about the state of the system and CPU up to the next level of firmware. This interface is achieved through the use of a set of defined SROM output parameters as described in Table C–1.
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Automatic CPU Speed Detection Table C–1 (Continued) Output Parameter Descriptions Output Parameter Parameter Description r19 (a3)—Signature and system revision ID This register includes a signature that specifies that the transfer is following the standard protocol and that the other values can be trusted. In addition, the signature can identify which version of the protocol is being followed.
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Memory Initialization C.4 Memory Initialization Eight consecutive row address strobe (RAS) cycles are performed to the system memory bank to “wake up” the DRAMs. This is done by reading the bank eight times. The caches are disabled at this point so the read data goes directly to the DRAMs (except for the Scache, which cannot be turned off). Good data parity is ensured by writing all memory locations. This is done by rewriting the full contents of memory with the same data.
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Special ROM Header C.6 Special ROM Header The MAKEROM tool is used to place a special header on ROM image files. The SROM allows the system (flash) ROM to contain several different ROM images, each with its own header. The header informs the SROM where to load the image, and whether or not it has been compressed with the MAKEROM tool. The header is optional for system ROMs containing a single image.
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Special ROM Header Table C–2 describes each entry in the special header. Table C–2 Special Header Entry Descriptions C–6 Entry Description Validation and inverse validation pattern This quadword contains a special signature pattern used to validate that the special ROM header has been located. The pattern is 5A5AC3C3A5A53C3C. Header size (bytes) This longword provides the size of the header block, which varies among versions of the header specification.
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Special ROM Header Table C–2 (Continued) Special Header Entry Descriptions Entry Description Firmware ID The firmware ID is a byte that specifies the firmware type. This information facilitates image boot options necessary to boot different operating systems.
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Flash ROM Loading C.7 Flash ROM Loading Under normal conditions, the AlphaPC 164 loads and executes the second firmware image that it finds in the flash. If jumper CF7 is installed, the first firmware image will be loaded. This process begins with a search for the header signature beginning at the first location in the flash. Once the appropriate header is found, based on its ordinal position in the flash, the header checksum is validated.
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Flash ROM Access C.8 Flash ROM Access The flash ROM can be viewed as two banks of 512KB each. At power-up the lower 512KB bank is accessed by using the address range 86.FFF8.0000 to 86.FFFF.FFFF. Setting address bit 19 (flash_adr19) allows you to access the higher 512KB of flash ROM. Write a 1 to the register at address 0x800 to set address bit 19. Manually deposit a 1 to address 0x800 or enter the following command from the debug monitor: > wb 800 1 The address range for the higher bank is 86.FFF8.
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Icache Flush Code C.9 Icache Flush Code The following code is loaded into memory after the system ROM image. The code is then executed to flush the SROM initialization code from the Icache. The SROM initialization code is loaded into the Icache and maps to memory beginning at address zero. 77FF0119 mt r31, flushIc C0000001 br r0, +4 .long destination 6C008000 ldl_p r0, 0x0 (r0) 47FF041F bis r31, 31, 31 47FF041F bis r31, 31, 31 . . (total of 44 bis instructions) .
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D Supporting Products This appendix lists sources for components and accessories, some of which are not included with the AlphaPC 164. Digital Equipment Corporation does not warrant components or accessories available from other vendors, or guarantee that they will function in all configurations. Clock Oscillators An Alpha microprocessor clock solution. Components are available from: Digital Equipment Corporation A complete kit of clock oscillators is available under PN 70-33058-01.
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CPU Frequency Oscillator Frequency 21164-366 21164-400 21164-433 21164-466 21164-500 36.66 MHz (default) 40.0 MHz 43.33 MHz 46.66 MHz 50.0 MHz Thermal Products A heat-sink and fan solution. Components included: heat sink, GRAFOIL pad, two hex nuts, heat-sink clips, 60-mm fan, fan guard, and four screws. Components are available from: United Machine and Tool Design River Road Fremont NH 03044 Phone: 603.642.5040 Power Supply An ATX form-factor power supply, suitable for use with the AlphaPC 164 (+3.
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E Glossary and Acronyms This glossary provides definitions for terms and acronyms associated with the AlphaPC 164 motherboard and chips, specifically as applied to Alpha architecture. AlphaPC 164 An evaluation board. A hardware/software application development platform for the Digital Semiconductor 21164 microprocessor and Digital Semiconductor 21172 core logic chipset program. ASIC Application-specific integrated circuit. Bcache Backup cache.
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bus A group of signals that consists of many transmission lines or wires. It interconnects computer-system components to provide communications paths for addresses, data, and control information. The buses used in the AlphaPC 164 include PCI64, PCI32, and ISA. cache memory A small, high-speed memory placed between slower main memory and the processor. A cache increases effective memory transfer rates and processor speed.
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EBSDK Evaluation board software design kit. ECC Error correction code. A 16-bit ECC is passed on the 21164 microprocessor’s data_check lines for each 128-bit data transfer. flash ROM Flash read-only memory. On the AlphaPC 164, a 1MB, nonvolatile, writable ROM. Icache Instruction cache. An 8KB L1 cache reserved for instructions on the 21164 microprocessor chip. IPR Internal processor register. ISA Industry Standard Architecture.
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PGA Pin grid array. PLA Programmable logic array. PLD Programmable logic device. PLL Phase-locked loop. PQFP Plastic quad flat pack. primary cache The cache that is the fastest and closest to the processor. The 21164 microprocessor contains instruction, data, and unified instruction and data caches. Also called L1 cache. RAM Random-access memory. RAS Row address strobe. region One of four areas in physical memory space based on the two most significant, implemented, physical address bits.
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RISC Reduced instruction set computing. A computing system architecture with an instruction set that is paired down and reduced in complexity so that most instructions can be performed in a single processor cycle. High-level compilers synthesize the more complex, least frequently used instructions by breaking them down into simpler instructions. This approach allows the RISC architecture to implement a small, hardware-assisted instruction set, thus eliminating the need for microcode. Scache Secondary cache.
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write-through cache A cache in which copies are kept of any data in the region. Read operations may use the copies, but write operations update the actual data location and either update or invalidate all copies.
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F Support, Products, and Documentation If you need technical support, a Digital Semiconductor Product Catalog, or help deciding which documentation best meets your needs, visit the Digital Semiconductor World Wide Web Internet site: http://www.digital.
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Digital Semiconductor Documentation The following table lists some of the available Digital Semiconductor documentation. For a complete list, contact the Digital Semiconductor Information Line.
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Ordering Third–Party Documentation You can order the following third-party documentation directly from the vendor: Title Vendor PCI Local Bus Specification, Revision 2.1 PCI Special Interest Group U.S. 1.800.433.5177 International 1.503.797.4207 FAX 1.503.234.6762 PCI System Design Guide PCI Special Interest Group (See previous entry.) 82420/82430 PCIset ISA and EISA Bridges (includes 82378IB/ZB SIO) PN 290483 Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect IL 60056 USA 1.800.628.
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Index Numerics C 21164 Cbox IPR space, B–20 21172 core logic chipset. See Chipset. 21172-BA. See DSW. 21172-CA. See CIA. 37C935. See Combination controller. 82378ZB. See SIO. CAS, 4–5, 4–6 Caution, xiii Chipset, 1–3, 4–3 CIA, 4–3, 4–5 CSR address space main, B–15 memory control, B–16 PCI address translation map space, B–17 Clocks, 1–5 14.
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keyboard, 2–11 microprocessor fan, 2–12 mouse, 2–11 parallel bus, 2–10 PCI bus, 2–7 pinouts, 2–7 to 2–13 speaker, 2–12 SROM test data, 2–11 Conventions numbering, xiv Current dc ampere requirements, 3–1 D DAC, A–32 Data field size, xiii Data units, xiv dc input power connector pinouts, 2–12 dc power requirements, 3–1 Debug monitor system support, 1–7 Dense memory space, A–10, B–10 Design support, 1–8 Dimensions, 3–2 Direct mapping, 4–5, A–29, A–32, A–34 Diskette controller, 4–9 Diskette drive connector pin
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J Jumper configurations, 2–4 Jumpers, 2–3 Bcache size, 2–6 Bcache speed, 2–6 boot option, 2–6 clock divisor, 2–6 flash ROM update, 2–7 memory bus width, 2–5 Mini-Debugger, 2–6 K Keyboard connector pinouts, 2–11 controller, 4–9 M Memory mode, 4–6 Memory subsystem, 1–3 Mini-Debugger, 4–24 Mouse connector pinouts, 2–11 controller, 4–9 N bridge, 4–8 bus, 4–6 connector pinouts, 2–7 speed, 4–7 configuration address space, B–13 dense memory space, B–10 devices, 4–6 expansion slots, 4–8 interface, 1–4 sparse I/
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Software support, 1–7 Sparse I/O space, A–17, B–1 memory space, A–12, B–1 Speaker connector pinouts, 2–12 Special cycle, A–25 SRM Console, 1–8 SROM, 1–5, 4–21, 4–24 code system support, 1–7 system initialization, C–1 test data connector pinouts, 2–11 Support, F–1 System components and features, 1–1 environment, B–1 software, 4–24 support, 1–7 T Target windows, A–29 Technical support, F–1 Time-of-year clock, 4–9 TLB, 4–5, A–37 hit, A–39 miss, A–39 Translation lookaside buffer. See TLB.