User`s guide

i.MX53 Layout Recommendations
i.MX53 System Development User’s Guide, Rev. 1
Freescale Semiconductor 2-27
• Decouple using distributed 0.01 μF and 0.1 μF capacitors by the regulator, controller, and devices.
• Place one 0.1 μF near the source of VREF, one near the VREF pin on the controller, and two
between the controller and the devices.
The following recommendations apply to the VTT voltage reference plane.
• Place the VTT island on the component side layer at the end of the bus behind the DRAM devices.
• Use a wide-island trace for current capacity.
• Place VTT generator as close to termination resistors as possible to minimize impedance
(inductance).
• Place one or two 0.1 μF decoupling capacitor by each termination RPACK on the VTT Island to
minimize the noise on VTT. Other bulk (10–22 μF) decoupling is also recommended to be placed
on the VTT Island.
2.7 TV Encoder Recommendations
Use the following recommendations for the TV encoder.
• For the TV/VGA interface, the IOR, IOG, and IOB signals must have 75-Ω imepedance.
2.8 SATA Recommendations
Use the following recommendations for the SATA.
• SATA differential pairs should have a differential impedance of 100.
• Each differential pair should be length matched to ± 5 mils.
• Follow standard high-speed differential routing rules for signal integrity.
2.9 LVDS Recommendations
Use the following recommendations for the LVDS.
• Follow standard high-speed differential routing rules for signal integrity.
• Each differential pair should be length matched to ± 5 mils.