User`s guide

i.MX53 Layout Recommendations

i.MX53 System Development User’s Guide, Rev. 1

2-18 Freescale Semiconductor

Table 2-3 shows the total etch of the signals for the byte 0 and byte 1 groups.

Table 2-3. Total Signal Etch (DDR2)

Layout is an example, using 1000 mils for the clock.

Signals Length (Mils)

DRAM_D0 667.16

DRAM_D1 663.66

DRAM_D2 666.01

DRAM_D3 663.89

DRAM_D4 662.69

DRAM_D5 663.41

DRAM_D6 668.31

DRAM_D7 664.02

DRAM_DQM0 663.5

DRAM_SDQS0 663.62

DRAM_SDQS0_B 668.24

DRAM_D8 668.57

DRAM_D9 663.69

DRAM_D10 664.28

DRAM_D11 666.39

DRAM_D12 664.75

DRAM_D13 668.45

DRAM_D14 664.65

DRAM_D15 663.07

DRAM_DQM1 664.08

DRAM_SDQS1 667.66

DRAM_SDQS1_B 663.07

DRAM_SDCLK0 1657.15

DRAM_SDCLK0_B 1655.22

DRAM_SDCLK1 1657

DRAM_SDCLK1_B 1658.81