User`s guide

i.MX53 Layout Recommendations
i.MX53 System Development User’s Guide, Rev. 1
2-6 Freescale Semiconductor
and keep the propagation delay to the minimum. Follow the reference board layout as a guideline for
memory placement and routing.
Figure 2-7 shows the final placement of the memories and the decoupling capacitors. The blue figure
shows the top layer and the red figure shows the bottom layer.
Figure 2-7. Final Placement of Memories and Decoupling Capacitors
2.4 DDR2 and DDR3 Routing Rules
DDR2 and DDR3 routing can be accomplished two different ways: routing all signals at the same length
or routing by byte group.
Routing all signals at the same length can be more difficult at first because of the tight space between the
DDR and the processor and the large number of required interconnects. However, it is the better way
because it makes signal timing analysis straightforward. Table 2-1 explains how to route the signals by the
same length.
Table 2-1. DDR2/DDR3 Routing by the Same Length
Signals Length Considerations
Address and Bank Clock length Match the signals ± 25 mils of the value
specified in the length column
Data and Buffer Clock length
Control signals Clock length
Clock Lcritical (3 inches) Match the signals of clocks signals ± 5
mils.
DQS and DQS_B Clock length Match the signals of DQS signals ± 10
mils of the value specified in the length
column.