User`s guide

Design Checklist
i.MX53 System Development User’s Guide, Rev. 1
Freescale Semiconductor 1-5
25. USB I/O D+, D–, and UID contacts on the i.MX device
require external ESD (electro-static discharge) damage
protection.
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Power Recommendations
26. Comply with the power-up and power-down
sequence guidelines as described in the data sheet to
guarantee reliable operation of the device.
Any deviation from these sequences may result in the
following situations:
• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the i.MX53 processor
(worst-case scenario)
27. Bypass both VDD_DIG_PLL (sourced from the
on-chip 1.2 V linear regulator) and VDD_ANA_PLL
(sourced from the on-chip 1.8 V linear regulator) with
separate ≥10 μF low-ESR capacitors to GND.
There is no need to drive these supplies externally, and
external supplies are not recommended due to possible
noise introduction, power-up sequence issues, or other
complications. The bypass capacitor must be included
whether VDD_DIG_PLL or VDD_ANA_PLL is sourced
on-chip or driven externally.
Refer to the data sheet for the applicable external supply
levels (if driven externally). A 0.1 μf or 0.22 μF capacitor
can be added in parallel to each larger capacitor when an
external voltage source is used. The 10 μF minimum
value must take into account temperature and expected
capacitor aging.
28. VDD_REG must be decoupled with a 22 μF capacitor
to GND. Mount the VDD_REG capacitor close to the
associated BGA ball. If two capacitors are utilized, mount
the smaller capacitor (such as 0.22 μF) closer to the
associated ball.
VDD_REG is the power supply input for the on-chip linear
voltage regulators that supply the PLL digital and analog
sections.
29. To configure CKIL and ECKIL as an oscillator, tie a
32.768 kHz crystal with <70 kΩ ESR (equivalent series
resistance) and approximately 9 pF load between CKIL
and ECKIL. Do not use an external biasing resistor.
The capacitors implemented on either side of the crystal
are about twice the crystal load capacitor. To hit the target
oscillation frequency, board capacitors need to be
reduced to compensate for board and chip parasitic
capacitance, so 15–16 pF could be employed. The
integrated oscillation amplifier has an on-chip self-biasing
scheme, but is high-impedance (relatively weak) to
minimize power consumption.
Care must be taken to limit parasitic leakage from CKIL
and ECKIL to either power or ground (> 20 MΩ) as this
negatively affects the amplifier bias and causes a
reduction of startup margin.
Use short traces between the crystal and the processor,
with a ground plane under the crystal, load capacitors,
and associated traces.
Typically CKIL and ECKIL should bias to approximately
0.5 V
Table 1-1. Design Checklist (continued)
Check
Box
Recommendation Explanation/Supplemental Recommendations