User`s guide

Supporting the i.MX53 Camera Sensor Interface CSI0
i.MX53 System Development User’s Guide, Rev. 1
Freescale Semiconductor 20-13
Section 20.7.3, “Timing Data Mode Protocols,” explains how the timing data mode protocols use these
signals. Not all signals are used in each timing data mode protocol.
20.7.3 Timing Data Mode Protocols
The CSI interface supports the following four timing/data protocols:
• Gated mode
• Non-gated mode
• BT.656 (Progressive and interlaced)
• BT.1120 (Progressive and interlaced)
In gated mode, VSYNC is used to indicate beginning of a frame, and HSYNC is used to indicate the
beginning of a raw. The sensor clock is always ticking.
In non-gated mode, VSYNC is used to indicate beginning of a frame, and HSYNC is not used. The sensor
clock only ticks when data is valid.
In BT.656 mode, the CSI works according to recommendation ITU-R BT.656. The timing reference
signals (frame start, frame end, line start, line end) are embedded in the data bus input.
In BT1120 mode, the CSI works according to recommendation ITU-R BT.1120. The timing reference
signals (frame start, frame end, line start, line end) are embedded in the data bus input.
For details, refer to the i.MX53 Applications Processor Reference Manual.
DATA_EN CSI0_DATA_EN Data Enable or Data ready
DATA[19:10] CSI0_DAT [19:10] Pixel data bus, optional to [19:4]
Table 20-3. CSI0 Parallel Interface Signals (continued)
Signal IPU Pin Description