User`s guide

Connecting an LVDS Panel to an i.MX53 Reference Board
i.MX53 System Development User’s Guide, Rev. 1
19-4 Freescale Semiconductor
19.3.1 Input Parallel Display Ports
The LDB is configurable to support either one or two (DI0, DI1) parallel RGB input ports. The LDB only
supports synchronous access mode.
Each RGB data interface contains the following:
• RGB data of 18 or 24 bits
• Pixel clock
• Control signals
— HSYNC, VSYNC, DE, and one additional optional general purpose control
— Transfers a total of up to 28 bits per data interface per pixel clock cycle
The LVDS supports the following data rates:
• For dual-channel output: up to 170 MHz pixel clock (e.g. UXGA—1600 × 1200 at 60 Hz + 35%
blanking)
• For single-channel output: up to 85 MHz per interface. (e.g. WXGA—1366 × 768 at 60 Hz + 35%
blanking).
19.3.2 Output LVDS Ports
The LDB has two LVDS channels, which are used to communicate RGB data and controls to external LCD
displays either through the LVDS interface or through LVDS receivers. Each channel consists of four data
pair and one clock pair, with a pair meaning an LVDS pad that contains PadP and PadM.
The LVDS ports may be used as follows:
• One single-channel output
• One dual channel output: single input, split to two output channels
• Two identical outputs: single input sent to both output channels
• Two independent outputs: two inputs sent, each to a different output channel
19.4 Further Reading
Please consult the following reference materials for additional information:
• i.MX53 Multimedia Applications Processor Reference Manual
• i.MX53 START Linux Reference Manual, included as part of the Linux BSP