User`s guide

Supporting the i.MX53 Reference Board DISP0 LCD
i.MX53 System Development User’s Guide, Rev. 1
18-4 Freescale Semiconductor
Figure 18-2 shows the interface between an i.MX53-based board and Chunghwa CLAA057VA01CT 5.7”
VGA LCD.
Figure 18-2. Interface
The LCD panel requires HSYNC, VSYNC, DE, PIXCLK, and part of the RGB data interface
(DISPB_DATA[17:0]). No additional signals, such as a reset signal or serial interface initialization routine
commands (SPI or I2C), are required. The backlight unit is controlled by a GPIO signal generated by the
i.MX53 (PWM), and the PMIC controls the touch panel interface. The display card includes a connection
for this panel.
Table 18-2 shows the timing parameters.
Table 18-2. Timing Parameters
Parameter Symbol Min Typ Max Unit
Screen Height or vertical period VP 515 525 560 Line
VSYNC pulse width VSW 1 1 1 Line
Vertical back porch VBP 34 34 34 Line
Vertical front porch VFP 1 11 46 Line