User`s guide

Supporting the i.MX53 Reference Board DISP0 LCD
i.MX53 System Development User’s Guide, Rev. 1
18-2 Freescale Semiconductor
18.1 Supported Display Interfaces
The i.MX53 processor supports the display interfaces shown in Figure 18-1.
Figure 18-1. Available Display Interfaces
Table 18-1 describes the available interfaces.
Table 18-1. Available Interfaces
Feature IPU (in i.MX53)
Number of ports Two: Full dual-display support
Legacy I/F Parallel and serial.
Synchronous (for display refresh) and asynchronous (to memory)
Very flexible—glue-less connection to RAM-less displays, display controllers, and TV
encoders.
MIPI/DSI high-speed I/F Full Support
Up to 2 lanes, 800 Mbps per lane
Analog TV-out
(composite, S-video, component)
Driven by TVE (Not supported on TO1)
Up to 720p at 60 fps or 1080i at 30 fps
(720p: 1280x720, 1080i: 1920x1080)