User`s guide

Using the Clock Connectivity Table
i.MX53 System Development User’s Guide, Rev. 1
Freescale Semiconductor 8-3
Clock gating is done with the low power clock gating (LPCG) module based on a combination of the clock
enable signals. For more information about how the clock gating signals are logically combined, refer to
the LPCG section in the CCM chapter of the i.MX53 reference manual.
NOTE
In some cases, a clock is part of a protocol and is sourced from a pad (mainly
through IOMUX). Such clocks do not appear in the clock connectivity table.
They are found in the “External Signals and Pin Multiplexing” chapter.