User`s guide

Using the Clock Connectivity Table
i.MX53 System Development User’s Guide, Rev. 1
8-2 Freescale Semiconductor
Clock connectivity is described in the in the “System Clocks Connectivity” section in the CCM chapter of
the i.MX53 reference manual. This section contains a series of tables that describe the clock inputs of each
module and which clock is connected to it. In most cases, the clocks are CCM root clocks as listed in
Table 8-1. However, some clocks come from IO pins (mainly though IOMUX) and not from CCM.
ssi1_clk_root Root for SSI-1 clock 66.5
ssi2_clk_root Root for SSI-2 clock 66.5
ssi3_clk_root Root for SSI-3 clock 66.5
usb_phy_clk_root Root for USB_PHY (24 Mhz) 24
ieee_cemx_clk_root Root for IEEE RTC clock 66.5
tve_216_54_clk_root Root for TVE (216/54 Mhz) 297
di0_clk_root Root for DI0 clock (for IPU) 170
di1_clk_root Root for DI1 clock (for IPU) 170
ipg_clk_sync_ieee_root Root for sync signal of IEEE RTC
module
66.5
ldb_di0_serial_clk_root Root clock for LDB bridge 595
ldb_di1_serial_clk_root Root clock for LDB bridge 595
ecspi_clk_root Root for CSPI clock 66.5
uart_clk_root Root for UART perclk 66.5
ipu_hsp_clk_root Root for IPU_HSP clock 200
gpu_clk_root Root for GPU clock 200
gpu2d_clk_root Root for GPU2D clock 200
esai_clk_root Root for ESAI serial clock 66.5
can_clk_root Root for FLEXCAN serial clock 66.5
pgc_clk_root Root for PGC clock of GPC 66.5
wrck_clk_root Root for WRCK clock 25
firi_clk_root Root for FIRI clock 66.5
ckil_sync_clk_root Root for CKIL clock after sync 0.032
Table 8-1. Clock Roots (continued)
Clock Root Name (from CCM) Description Target Frequency [MHz]