User`s guide

Interfacing DDR2 and DDR3 Memories with the i.MX53 Processor
i.MX53 System Development User’s Guide, Rev. 1
Freescale Semiconductor 6-11
The SCh has a 32 bit data bus. Therefore, DSIZ = 32 bit width.
Enable the SDRAM controller as follows:
setmem /32 0x63FD9000 = 0xC3190000
6.5.2 Power Down Register
Figure 6-5 shows the power down register’s bit fields, access, and reset values.
Values are as follows:
•tCKE = 3CK
• tCKSRE = greater than 5 CK
• tCKSRX = greater than 5 CK
Enable as follows:
setmem /32 0x63FD9004 = 0x0002002D
6.5.3 Timing Configuration 0 Register
Figure 6-6 shows the timing configuration 0 register’s bit fields, access, and reset values.
Values are as follows:
• tRFC = 86 CK
• tXS = tRFC + 10 ns = 90 CK
• tXP = greater of 3 CK
Access: Read/Write
31 28 27 24 23 19 18 16
R
PRCT_1 PRCT_0 — tCKE
W
Reset00000000 0 0000011
15 12 11 8 7 6 5 3 2 0
R
PWDT_1 PWDT_0
SLOW_
PD
BOTH
_CS_
PD
tCKSRX tCKSRE
W
Reset00000000 0 0010010
Figure 6-5. Power Down Register
Access: Read/Write
31 24 23 16 15 13 12 9 8 4 3 0
R
tRFC tXS tXP tXPDLL tFAW tCL
W
Reset00110010001101100010010011010011
Figure 6-6. Timing Configuration 0 Register