User`s guide

Interfacing DDR2 and DDR3 Memories with the i.MX53 Processor
i.MX53 System Development User’s Guide, Rev. 1
Freescale Semiconductor 6-9
setmem /32 0x53fa8564 = 0x00300040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
setmem /32 0x53fa8580 = 0x00300040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
// Initialize DDR3 memory - Micron MT41J128M16-187E
//** Keep for now, same setting as CPU3 board **//
//setmem /32 0x63fd904c = 0x01680172 //write leveling reg 0
//setmem /32 0x63fd9050 = 0x0021017f //write leveling reg 1
setmem /32 0x63fd9088 = 0x32383535 //read delay lines
setmem /32 0x63fd9090 = 0x40383538 //write delay lines
//setmem /32 0x63fd90F8 = 0x00000800 //Measure unit
setmem /32 0x63fd907c = 0x0136014d //DQS gating 0
setmem /32 0x63fd9080 = 0x01510141 //DQS gating 1
//* CPU3 Board setting
// Enable bank interleaving, Address mirror on, WALAT = 0x1, RALAT = 0x5, DDR2_EN = 0
//setmem /32 0x63fd9018 = 0x00091740 //Misc register:
//* Quick Silver board setting
// Enable bank interleaving, Address mirror off, WALAT = 0x1, RALAT = 0x5, DDR2_EN = 0
setmem /32 0x63fd9018 = 0x00011740 //Misc register
// Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
setmem /32 0x63fd9000 = 0xc3190000 //Main control register
// tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck
setmem /32 0x63fd900C = 0x555952E3 //timing configuration Reg 0.
// tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck
setmem /32 0x63fd9010 = 0xb68e8b63 //timing configuration Reg 1
// tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4
setmem /32 0x63fd9014 = 0x01ff00db //timing configuration Reg 2
setmem /32 0x63fd902c = 0x000026d2 //command delay (default)
setmem /32 0x63fd9030 = 0x009f0e21 //out of reset delays
// Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values
setmem /32 0x63fd9008 = 0x12273030 //ODT timings
// tCKE=3; tCKSRX=5; tCKSRE=5
setmem /32 0x63fd9004 = 0x0002002d //Power down control
//**********************************
//DDR device configuration:
//**********************************
//**********************************
// CS0:
//**********************************
setmem /32 0x63fd901c = 0x00008032 //write mode reg MR2 with cs0 (see below for settings)
// Full array self refresh
// Rtt_WR disabled (no ODT at IO CMOS operation)
// Manual self refresh
// CWS=5
setmem /32 0x63fd901c = 0x00008033 //write mode reg MR3 with cs0 .
setmem /32 0x63fd901c = 0x00028031 //write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see
below for settings)
// out impedance = RZQ/7
// Rtt_nom disabled (no ODT at IO CMOS operation)
// Aditive latency off
// write leveling disabled
// tdqs (differential?) disabled