User`s guide

Interfacing DDR2 and DDR3 Memories with the i.MX53 Processor
i.MX53 System Development User’s Guide, Rev. 1
6-8 Freescale Semiconductor
//*==========================================================================================
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setmem /32 0x53fd4068 = 0xffffffff
setmem /32 0x53fd406c = 0xffffffff
setmem /32 0x53fd4070 = 0xffffffff
setmem /32 0x53fd4074 = 0xffffffff
setmem /32 0x53fd4078 = 0xffffffff
setmem /32 0x53fd407c = 0xffffffff
setmem /32 0x53fd4080 = 0xffffffff
setmem /32 0x53fd4084 = 0xffffffff
//*==========================================================================================
======
// Initialization script for 32 bit DDR2 (CS0+CS1)
//*==========================================================================================
======
// DDR3 IOMUX configuration
//* Global pad control options */
setmem /32 0x53fa86f4 = 0x00000000 //IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2,
0=CMOS mode
setmem /32 0x53fa8714 = 0x00000000 //IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS
mode
setmem /32 0x53fa86fc = 0x00000000 //IOMUXC_SW_PAD_CTL_GRP_DDRPKE
setmem /32 0x53fa8724 = 0x04000000 //IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=10
// setmem /32 0x53fa8724 = 0x00000000 //IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00
// setmem /32 0x53fa8724 = 0x02000000 //IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=01
// setmem /32 0x53fa8724 = 0x06000000 //IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=11
//* Data bus byte lane pad drive strength control options */
setmem /32 0x53fa872c = 0x00300000 //IOMUXC_SW_PAD_CTL_GRP_B3DS
setmem /32 0x53fa8554 = 0x00300000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
setmem /32 0x53fa8558 = 0x00300040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
setmem /32 0x53fa8728 = 0x00300000 //IOMUXC_SW_PAD_CTL_GRP_B2DS
setmem /32 0x53fa8560 = 0x00300000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
setmem /32 0x53fa8568 = 0x00300040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
setmem /32 0x53fa871c = 0x00300000 //IOMUXC_SW_PAD_CTL_GRP_B1DS
setmem /32 0x53fa8594 = 0x00300000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
setmem /32 0x53fa8590 = 0x00300040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
setmem /32 0x53fa8718 = 0x00300000 //IOMUXC_SW_PAD_CTL_GRP_B0DS
setmem /32 0x53fa8584 = 0x00300000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
setmem /32 0x53fa857c = 0x00300040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
//* SDCLK pad drive strength control options */
setmem /32 0x53fa8578 = 0x00300000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
setmem /32 0x53fa8570 = 0x00300000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
//* Control and addr bus pad drive strength control options */
setmem /32 0x53fa8574 = 0x00300000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
setmem /32 0x53fa8588 = 0x00300000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
setmem /32 0x53fa86f0 = 0x00300000 //IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus
setmem /32 0x53fa8720 = 0x00300000 //IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0,
SDCKE1, SDWE