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Interfacing DDR2 and DDR3 Memories with the i.MX53 Processor
i.MX53 System Development User’s Guide, Rev. 1
Freescale Semiconductor 6-7
setmem /32 0x63fd901c = 0x0a528030 // BL = 4, CAS latency = 5, write recovery = 6
setmem /32 0x63fd901c = 0x03c68031
setmem /32 0x63fd901c = 0x00468031 // reduced drive strength, enable 50ohm ODT
setmem /32 0x63fd901c = 0x04008018
setmem /32 0x63fd901c = 0x0000803a
setmem /32 0x63fd901c = 0x0000803b
setmem /32 0x63fd901c = 0x00008039
setmem /32 0x63fd901c = 0x0b528138
setmem /32 0x63fd901c = 0x04008018
setmem /32 0x63fd901c = 0x00008028
setmem /32 0x63fd901c = 0x00008028
setmem /32 0x63fd901c = 0x0a528038 // BL = 4, CAS latency = 5, write recovery = 6
setmem /32 0x63fd901c = 0x03c68039
setmem /32 0x63fd901c = 0x00468039 // reduced drive strength, enable 50ohm ODT
setmem /32 0x63fd9020 = 0x00005800
setmem /32 0x63fd9058 = 0x00033337 // Enable 50ohm ODT
setmem /32 0x63fd901c = 0x00000000
6.4 Configuring the DDR3 JTAG Script
The following code shows an example of how to configure DDR3 memory for the i.MX53 processor:
Example 6-2. DDR3 JTAG Script Configuration
//*==========================================================================================
======
//* Copyright (C) 2010, Freescale Semiconductor, Inc. All Rights Reserved
//* THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
//* BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
//* Freescale Semiconductor, Inc.
//*==========================================================================================
======
// Initialization script for Rita Quick Silver Board, DDR3
// Version 1.0
//*==========================================================================================
======
wait = on
//*==========================================================================================
======
// init ARM
//*==========================================================================================
======
//*==========================================================================================
======
// Disable WDOG
//*==========================================================================================
======
setmem /16 0x53f98000 = 0x30
//*==========================================================================================
======
// Enable all clocks (they are disabled by ROM code)