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Interfacing DDR2 and DDR3 Memories with the i.MX53 Processor

i.MX53 System Development User’s Guide, Rev. 1

6-6 Freescale Semiconductor

setmem /32 0x53fa8554 = 0x00380000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3

setmem /32 0x53fa8558 = 0x00380040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3

setmem /32 0x53fa8560 = 0x00380000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2

setmem /32 0x53fa8564 = 0x00380040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1

setmem /32 0x53fa8568 = 0x00380040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2

setmem /32 0x53fa8570 = 0x00200000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk

to improve EVK DDR max frequency

setmem /32 0x53fa8574 = 0x00380000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS

setmem /32 0x53fa8578 = 0x00200000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0- boazp: weaker sdclk

to improve EVK DDR max frequency

setmem /32 0x53fa857c = 0x00380040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0

setmem /32 0x53fa8580 = 0x00380040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0

setmem /32 0x53fa8584 = 0x00380000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0

setmem /32 0x53fa8588 = 0x00380000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS

setmem /32 0x53fa8590 = 0x00380040 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1

setmem /32 0x53fa8594 = 0x00380000 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1

setmem /32 0x53fa86f0 = 0x00380000 //IOMUXC_SW_PAD_CTL_GRP_ADDDS

setmem /32 0x53fa86f4 = 0x00000200 //IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL

setmem /32 0x53fa86fc = 0x00000000 //IOMUXC_SW_PAD_CTL_GRP_DDRPKE

setmem /32 0x53fa8714 = 0x00000000 //IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode

setmem /32 0x53fa8718 = 0x00380000 //IOMUXC_SW_PAD_CTL_GRP_B0DS

setmem /32 0x53fa871c = 0x00380000 //IOMUXC_SW_PAD_CTL_GRP_B1DS

setmem /32 0x53fa8720 = 0x00380000 //IOMUXC_SW_PAD_CTL_GRP_CTLDS

setmem /32 0x53fa8724 = 0x06000000 //IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0

setmem /32 0x53fa8728 = 0x00380000 //IOMUXC_SW_PAD_CTL_GRP_B2DS

setmem /32 0x53fa872c = 0x00380000 //IOMUXC_SW_PAD_CTL_GRP_B3DS

// Initialize DDR2 memory - Hynix H5PS2G83AFR

setmem /32 0x63fd9088 = 0x2b2f3031

setmem /32 0x63fd9090 = 0x40363333

setmem /32 0x63fd9098 = 0x00000f00 //boazp: add 3 logic unit of delay to sdclk to improve EVK

DDR max frequency

setmem /32 0x63fd90F8 = 0x00000800

setmem /32 0x63fd907c = 0x01310132

setmem /32 0x63fd9080 = 0x0133014b

// Enable bank interleaving, RALAT = 0x3, DDR2_EN = 1

setmem /32 0x63fd9018 = 0x000016d0

// Enable CSD0 and CSD1, row width = 15, column width = 10, burst length = 4, data width = 32bit

setmem /32 0x63fd9000 = 0xc4110000

// tRFC = 78 ck, tXS = 82 ck, tXP = 2 ck, tXPDLL(tXARD) = 2 ck, tFAW = 14 ck, CAS latency = 5 ck

setmem /32 0x63fd900C = 0x4d5122d2

// tRCD = 5 ck, tRP = 5 ck, tRC = 23 ck, tRAS = 18 ck, tRPA = 1, tWR = 6 ck, tMRD = 2 ck, tCWL = 4 ck

setmem /32 0x63fd9010 = 0x92d18a22

// tDLLK(tXSRD) = 200 cycles, tRTP = 3 ck, tWTR = 3ck, tRRD = 3ck

setmem /32 0x63fd9014 = 0x00c70092

setmem /32 0x63fd902c = 0x000026d2

setmem /32 0x63fd9030 = 0x009f000e

setmem /32 0x63fd9008 = 0x12272000

setmem /32 0x63fd9004 = 0x00030012

setmem /32 0x63fd901c = 0x04008010

setmem /32 0x63fd901c = 0x00008032

setmem /32 0x63fd901c = 0x00008033

setmem /32 0x63fd901c = 0x00008031

setmem /32 0x63fd901c = 0x0b5280b0

setmem /32 0x63fd901c = 0x04008010

setmem /32 0x63fd901c = 0x00008020