User`s guide

Interfacing DDR2 and DDR3 Memories with the i.MX53 Processor
i.MX53 System Development User’s Guide, Rev. 1
Freescale Semiconductor 6-5
wait = on
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// init ARM
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//*==========================================================================================
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// Disable WDOG
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setmem /16 0x53f98000 = 0x30
//*==========================================================================================
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// Program PLL2 to 300MHz
//*==========================================================================================
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setmem /32 0x63f84004 = 0x4 // disable PLL2 automatic restart
setmem /32 0x63f84000 = 0x1222
setmem /32 0x63f8400c = 0x3e7
setmem /32 0x63f84010 = 0xfa
setmem /32 0x63f84008 = 0x60
setmem /32 0x53fd4018 = 0x00015154
setmem /32 0x53fd4014 = 0x03119184 // switch peripherals to PLL3
pause 1
setmem /32 0x63f84000 = 0x1232 // restart PLL2
pause 1
setmem /32 0x53fd4014 = 0x01119184
setmem /32 0x53fd4018 = 0x00016154 // switch peripherals back to PLL2
pause 1
setmem /32 0x63f84004 = 0x6 // re-enable PLL2 automatic restart
//*==========================================================================================
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// Enable all clocks (they are disabled by ROM code)
//*==========================================================================================
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setmem /32 0x53fd4068 = 0xffffffff
setmem /32 0x53fd406c = 0xffffffff
setmem /32 0x53fd4070 = 0xffffffff
setmem /32 0x53fd4074 = 0xffffffff
setmem /32 0x53fd4078 = 0xffffffff
setmem /32 0x53fd407c = 0xffffffff
setmem /32 0x53fd4080 = 0xffffffff
setmem /32 0x53fd4084 = 0xffffffff
//*==========================================================================================
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// Initialization script for 32 bit DDR2 (CS0+CS1)
//*==========================================================================================
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// DDR2 IOMUX configuration