User`s guide

Interfacing DDR2 and DDR3 Memories with the i.MX53 Processor
i.MX53 System Development User’s Guide, Rev. 1
6-4 Freescale Semiconductor
Figure 6-3. DDR3 Memory Connection
6.3 Configuring the DDR2 JTAG Script
The following code shows an example of how to configure the DDR2 memory for the i.MX53 processor:
Example 6-1. DDR2 JTAG Script Configuration
//*==========================================================================================
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//* Copyright (C) 2010, Freescale Semiconductor, Inc. All Rights Reserved
//* THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
//* BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
//* Freescale Semiconductor, Inc.
//*==========================================================================================
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// Initialization script for Rita CPU2 Board
// Version 1.0
//*==========================================================================================
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