User`s guide

Interfacing DDR2 and DDR3 Memories with the i.MX53 Processor
i.MX53 System Development User’s Guide, Rev. 1
Freescale Semiconductor 6-3
6.2 i.MX53 Memory Interface
Figure 6-2 shows the DDR2 connection. The DDR2 device is the H5PS2G83AFR.
Figure 6-2. DDR2 Memory Connection
Figure 6-3 shows the DDR3 memory connections. The DDR3 device is the EDJ2116DASE.
The DDR2 and DDR3 memory connections differ in the following ways:
• RESET and VREF signals.
• DDR3 DQS signals are connected as differential pairs to the memory.