User`s guide

Interfacing DDR2 and DDR3 Memories with the i.MX53 Processor
i.MX53 System Development User’s Guide, Rev. 1
6-2 Freescale Semiconductor
Figure 6-1 shows the block diagram of the DDR2/DDR3 interfaced with the i.MX53 from the reference
design boards.
Figure 6-1. Connection Between i.MX53 Processor and DDR2 and DDR3
i. MX53
A[15:0]
 DRAM_D[31:0]
CS0/CS1
CKE0,SDCL K0,SDCLK0_B
CKE1,SDCL K1,SDCLK1_B

 SDWE…

DDR2
/
3
A[13:0]
SD[31:0]
CS0
CLK…
WE…
DDR2
/
3
A[13:0]
SD[31:0]
CS1
CLK…
WE…