User`s guide

i.MX53 System Development User’s Guide, Rev. 1
Freescale Semiconductor xi
Figures
Figure
Number Title
Page
Number
Figures
1-1 Boot Configuration Bus Isolation Resistors............................................................................ 1-8
2-1 i.MX53 Ball-Grid Array ......................................................................................................... 2-1
2-2 i.MX53 Package Information.................................................................................................. 2-2
2-3 i.MX53 Fanouts ...................................................................................................................... 2-3
2-4 Layer Stack.............................................................................................................................. 2-4
2-5 Stackup Requirements............................................................................................................. 2-4
2-6 Connection Between i.MX53 and DDR2 and DDR3 ............................................................. 2-5
2-7 Final Placement of Memories and Decoupling Capacitors..................................................... 2-6
2-8 Topology for ADDR/CMD/CTRL Signals ............................................................................. 2-8
2-9 Topology of Data Group, Point-to-Point Connection ............................................................. 2-8
2-10 Topology for Data Bus of Two Byte Groups by Memory ...................................................... 2-9
2-11 Clock Routing Topology......................................................................................................... 2-9
2-12 ADDR/CMD Signal Routing................................................................................................ 2-10
2-13 CTRL Signal Topology......................................................................................................... 2-10
2-14 Data Bus Routing Topology.................................................................................................. 2-10
2-15 Clock Routing Topology....................................................................................................... 2-11
2-16 Top DDR2 Routing .............................................................................................................. 2-12
2-17 Internal 1 DDR2 Routing...................................................................................................... 2-13
2-18 Power Plane 1 DDR2 Routing ............................................................................................. 2-14
2-19 Power Plane 2 DDR2 Routing ............................................................................................. 2-15
2-20 Internal 2 DDR2 Routing ..................................................................................................... 2-16
2-21 Bottom DDR2 Routing ........................................................................................................2-17
2-22 Top 8-DDR3 Routing ........................................................................................................... 2-20
2-23 Internal 1 8-DDR3 Routing ..................................................................................................2-21
2-24 Power Plane 1 8-DDR3 Routing .......................................................................................... 2-22
2-25 Power Plane 2 8-DDR3 Routing........................................................................................... 2-23
2-26 Internal 2 8-DDR3 Routing ..................................................................................................2-24
2-27 Bottom 8-DDR3 Routing ..................................................................................................... 2-25
2-28 Microstrip and Stripline Differential Pair Dimensions ......................................................... 2-28
2-29 Differential Pair Routing....................................................................................................... 2-28
3-1 Model IV Keywords’ Structure............................................................................................... 3-4
3-2 Model Data Interpretation....................................................................................................... 3-6
3-3 Generic Test Load Network ....................................................................................................3-7
4-1 Application Window after Expanding UARTs 2 and 3 of i.MX35 TO2.1.............................. 4-2
4-2 Hovering Mouse over a Signal to Show Other Signals Sharing that Ball/Pin........................ 4-3
4-3 Hovering Mouse over a Signal in the Signals Tab.................................................................. 4-4
4-4 Expanding UART3_RTS to Show Potential Conflicts ........................................................... 4-5
4-5 Resolving Conflicts by Changing Ball Assignments.............................................................. 4-6
4-6 Signal Tab with Comment Entry Menu .................................................................................. 4-7
4-7 UART2_TXD_MUX with Note.............................................................................................. 4-8
4-8 File > Save Dialog Box, Showing the Three Formats for Saving Design Info....................... 4-9