User`s guide

Setting up Power Management
i.MX53 System Development User’s Guide, Rev. 1
5-8 Freescale Semiconductor
Figure 5-5 shows the power-up sequence of the interface that results from the connections shown in
Figure 5-3 and Figure 5-4.
Figure 5-5. Interface Power-up Sequence (DA9053)
i.MX53 Power Domains
PMIC Regulators

VDDA
VDDAL
VDD_ANA_PLL
NVCC_CKIH
NVCC_JTAG
NVCC_LVDS_BG
NVCC_NANDF
NVCC_CSI
NVCC_RESET
NVCC_XTAL
VDD_REG
NVCC_SRTC_POW
VCC
LDO1
VBUCKPRO
LDO10
LDO6
LDO8
VBUCKPERI
VDDGP
VDD_DIG_PLL
NVCC_EMI_DRAM
VP, VPH
NVCC_LVDS
USB_H1_VDDA25
USB_OTG_VDDA25
NVCC_LCD
TVDAC_DHVDD
TVDA
C
AHVDDR
G
B
VBUCKCORE
VBUCKMEM
VBUCKPERI_SW
LDO2
LDO5
LDO4
LDO7
LDO3
LDO9
USB_H1_VDDA33
USB_OTG_VDDA33
NVCC_SD1
NVCC_SD2
NVCC_PATA
NVCC_KEYPAD
NVCC_GPIO
NVCC_FEC
NVCC_EIM_MAIN
RT8010