Datasheet
Table Of Contents
- General Description
- Features
- Ordering Information
- Applications
- Key Specifications
- Functional Description
- Figure 2 Functional Block Diagram
- Image Sensor Array
- Analog Amplifier
- 10-Bit A/D Converters
- Channel Balance
- Black Level Compensation
- Windowing
- Timing Generator and Control Logic
- Digital Signal Processor (DSP)
- Output Formatter
- Compression Engine
- Microcontroller
- SCCB Interface
- Strobe Mode
- Reset
- Power Down Mode
- Digital Video Port
- Pin Description
- Electrical Characteristics
- Timing Specifications
- Figure 13 SCCB Interface Timing Diagram
- Table 9 SCCB InterfaceTiming Specifications
- Figure 14 UXGA, SVGA, and CIF Line/Pixel Output Timing
- Table 10 Pixel Timing Specifications
- Figure 15 UXGA Frame Timing
- Figure 16 SVGA Frame Timing
- Figure 17 CIF Mode Frame Timing
- Figure 18 Frame Exposure Mode Timing with EXPST_B Staying Low
- Figure 19 Frame Exposure Mode Timing with EXPST_B Asserted
- Table 11 Frame Exposure Timing Specifications
- OV2640 Light Response
- Register Set
- Package Specifications
- Revision History
Pin Description
Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 9
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E2 Y0 I/O
Video port output bit[0]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
E3 PCLK I/O
Pixel clock output
Default: Input
Note: There is no internal pull-up/pull-down resistor.
E4 EGND Ground Ground for internal regulator
E5 Y6 I/O
Video port output bit[6]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
E6 DGND Ground Ground for digital core
F1 EVDD Power Power for internal regulator
F2 DVDD Power Sensor digital power (Core)
F3 Y2 I/O
Video port output bit[2]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
F4 Y4 I/O
Video port output bit[4]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
F5 Y8 I/O
Video port output bit[8]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
F6 DVDD Power Sensor digital power (Core)
G1 EVDD Power Power for internal regulator
G2 DGND Ground Ground for digital core
G3 Y3 I/O
Video port output bit[3]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
G4 Y5 I/O
Video port output bit[5]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
G5 Y7 I/O
Video port output bit[7]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
G6 Y9 I/O
Video port output bit[9]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
Table 3 Pin Description
Pin Location Name Pin Type Function/Description