Datasheet

Functional Description
Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 7
O
mni ision
Line/Pixel Timing
The OV2640 digital video port can be programmed to
work in either master or slave mode.
In both master and slave modes, pixel data output is
synchronous with PCLK (or MCLK if port is a slave),
HREF, and VSYNC. The default PCLK edge for valid data
is the negative edge but may be programmed using
register COM10[4] for the positive edge. Basic line/pixel
output timing and pixel timing specifications are shown in
Figure 14 and Table 10.
Also, using register COM10[5], PCLK output can be gated
by the active video period defined by the HREF signal.
See Figure 11 for details.
Figure 11 PCLK Output Only at Valid Pixels
The specifications shown in Table 10 apply for
DVDD = +1.2 V, DOVDD = +2.8 V, T
A
= 25°C, sensor
working at 15 fps, external loading = 20 pF.
V
SYNC
P
CLK
H
REF
P
CLK
P
CLK active edge positive
P
CLK active edge negative
Pixel Output Pattern
Table 2 shows the output data order from the OV2640.
The data output sequence following the first HREF and
after VSYNC is: B
0,0
G
0,1
B
0,2
G
0,3
… B
0,1598
G
0,1599
.
After the second HREF the output is G
1,0
R
1,1
G
1,2
R
1,3
…
G
1,1598
R
1,1599
…, etc. If the OV2640 is programmed to
output SVGA resolution data, horizontal and vertical
sub-sampling will occur. The default output sequence for
the first line of output will be: B
0,0
G
0,1
B
0,4
G
0,5
… B
0,1596
G
0,1597
. The second line of output will be: G
1,0
R
1,1
G
1,4
R
1,5
… G
1,1596
R
1,1597
.
Table 2 Data Pattern
R/C 0 1 2 3 . . . 1598 1599
0 B
0,0
G
0,1
B
0,2
G
0,3
. . . B
0,1598
G
0,1599
1 G
1,0
R
1,1
G
1,2
R
1,3
. . . G
1,1598
R
1,1599
2 B
2,0
G
2,1
B
2,2
G
2,3
. . . B
2,1598
G
2,1599
3 G
3,0
R
3,1
G
3,2
R
3,3
. . . G
3,1598
R
3,1599
.
.
.
.
1198 B
1198,0
G
1198,1
B
1198,2
G
1198,3
. . . B
1198,1598
G
1198,1599
1199 G
1199,0
R
1199,1
G
1199,2
R
1199,3
. . . G
1199,1598
R
1199,1599