Datasheet
Table Of Contents
- General Description
- Features
- Ordering Information
- Applications
- Key Specifications
- Functional Description
- Figure 2 Functional Block Diagram
- Image Sensor Array
- Analog Amplifier
- 10-Bit A/D Converters
- Channel Balance
- Black Level Compensation
- Windowing
- Timing Generator and Control Logic
- Digital Signal Processor (DSP)
- Output Formatter
- Compression Engine
- Microcontroller
- SCCB Interface
- Strobe Mode
- Reset
- Power Down Mode
- Digital Video Port
- Pin Description
- Electrical Characteristics
- Timing Specifications
- Figure 13 SCCB Interface Timing Diagram
- Table 9 SCCB InterfaceTiming Specifications
- Figure 14 UXGA, SVGA, and CIF Line/Pixel Output Timing
- Table 10 Pixel Timing Specifications
- Figure 15 UXGA Frame Timing
- Figure 16 SVGA Frame Timing
- Figure 17 CIF Mode Frame Timing
- Figure 18 Frame Exposure Mode Timing with EXPST_B Staying Low
- Figure 19 Frame Exposure Mode Timing with EXPST_B Asserted
- Table 11 Frame Exposure Timing Specifications
- OV2640 Light Response
- Register Set
- Package Specifications
- Revision History
6 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006
OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™
O
mni ision
"1" and the OV2640 will use PWDN and RESETB pins as
vertical and horizontal synchronization triggers supplied
by a master device. The master device must provide the
following signals:
1. System clock MCLK to XVCLK pin
2. Horizontal sync MHSYNC to RESETB pin
3. Vertical frame sync MVSYNC to PWDN pin
See Figure 8 for slave mode connections and Figure 9 for
detailed timing considerations.
Figure 8 Slave Mode Connection
Figure 9 Slave Mode Timing
Strobe Mode
The OV2640 has a Strobe mode that allows it to work with
an external flash and LED.
Reset
The OV2640 includes a RESETB pin (pin C6) that forces
a complete hardware reset when it is pulled low (GND).
The OV2640 clears all registers and resets them to their
default values when a hardware reset occurs. A reset can
also be initiated through the SCCB interface.
Y[9:0]
RESETB
PWDN
XVCLK
MHSYNC
MVSYNC
MCLK
Master
Device
OV2640
NOTE:
1) T
HS
> 6 T
clk
, Tvs > T
line
2) T
line
= 1922 x T
clk
(UXGA); T
line
= 1190 x T
clk
(SVGA);
3) T
frame
= 1248 x T
line
(UXGA); T
frame
= 672 x T
line
(SVGA);
T
frame
= 336 x T
line
(CIF)
T
line
= 595 x T
clk
(CIF)
T
frame
T
VS
T
line
T
clk
T
HS
M
VSYNC
M
HSYNC
MCLK
Power Down Mode
Two methods are available to place the OV2640 into
power-down mode: hardware power-down and SCCB
software power-down.
To initiate hardware power-down, the PWDN pin (pin B6)
must be tied to high. When this occurs, the OV2640
internal device clock is halted and all internal counters are
reset. The current draw is less than 15 µA in this standby
mode.
Executing a software power-down through the SCCB
interface suspends internal circuit activity but does not
halt the device clock. The current requirements drop to
less than 1 mA in this mode. All register content is
maintained in standby mode.
Digital Video Port
MSB/LSB Swap
The OV2640 has a 10-bit digital video port. The MSB and
LSB can be swapped with the control registers. Figure 10
shows some examples of connections with external
devices.
Figure 10 Connection Examples
Y7
Y6
Y5
Y4
Y3
Y2
Y1
LSB Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
MSB Y0
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
External
Device
OV2640 Externa
l
Device
OV2640
MSB Y9
Y8
Y9
Y8
LSB Y9
Y8
Y0
Y1
Default 10-bit Connection Swap 10-bit Connection
Y7
Y6
Y5
Y4
Y3
Y2
Y1
LSB Y0
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
MSB Y0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
External
Device
OV2640 Externa
l
Device
OV2640
MSB Y9
Y8
Y7
Y6
LSB Y9
Y8
Default 8-bit Connection Swap 8-bit Connection