Datasheet
Table Of Contents
- General Description
- Features
- Ordering Information
- Applications
- Key Specifications
- Functional Description
- Figure 2 Functional Block Diagram
- Image Sensor Array
- Analog Amplifier
- 10-Bit A/D Converters
- Channel Balance
- Black Level Compensation
- Windowing
- Timing Generator and Control Logic
- Digital Signal Processor (DSP)
- Output Formatter
- Compression Engine
- Microcontroller
- SCCB Interface
- Strobe Mode
- Reset
- Power Down Mode
- Digital Video Port
- Pin Description
- Electrical Characteristics
- Timing Specifications
- Figure 13 SCCB Interface Timing Diagram
- Table 9 SCCB InterfaceTiming Specifications
- Figure 14 UXGA, SVGA, and CIF Line/Pixel Output Timing
- Table 10 Pixel Timing Specifications
- Figure 15 UXGA Frame Timing
- Figure 16 SVGA Frame Timing
- Figure 17 CIF Mode Frame Timing
- Figure 18 Frame Exposure Mode Timing with EXPST_B Staying Low
- Figure 19 Frame Exposure Mode Timing with EXPST_B Asserted
- Table 11 Frame Exposure Timing Specifications
- OV2640 Light Response
- Register Set
- Package Specifications
- Revision History
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REVISION CHANGE LIST
Document Title: OV2640 Datasheet Version: 1.5
DESCRIPTION OF CHANGES
The following changes were made to version 1.4:
• Under Register Set section on page 18, changed the second paragraph from
“There are two different sets for register address from 0x00 to 0x7E. Both register 0xF8
and register 0xFF control which set is accessible. When 0xF8=00 and 0xFF=00, Table 12
is effective. When 0xF8=01, 0xFF=7F, Table 13 is effective.”
to
“There are two different sets of register banks. Register 0xFF controls which set is
accessible. When register 0xFF=00, Table 12 is effective. When register 0xFF=01, Table
13 is effective.”