Datasheet
Table Of Contents
- General Description
- Features
- Ordering Information
- Applications
- Key Specifications
- Functional Description
- Figure 2 Functional Block Diagram
- Image Sensor Array
- Analog Amplifier
- 10-Bit A/D Converters
- Channel Balance
- Black Level Compensation
- Windowing
- Timing Generator and Control Logic
- Digital Signal Processor (DSP)
- Output Formatter
- Compression Engine
- Microcontroller
- SCCB Interface
- Strobe Mode
- Reset
- Power Down Mode
- Digital Video Port
- Pin Description
- Electrical Characteristics
- Timing Specifications
- Figure 13 SCCB Interface Timing Diagram
- Table 9 SCCB InterfaceTiming Specifications
- Figure 14 UXGA, SVGA, and CIF Line/Pixel Output Timing
- Table 10 Pixel Timing Specifications
- Figure 15 UXGA Frame Timing
- Figure 16 SVGA Frame Timing
- Figure 17 CIF Mode Frame Timing
- Figure 18 Frame Exposure Mode Timing with EXPST_B Staying Low
- Figure 19 Frame Exposure Mode Timing with EXPST_B Asserted
- Table 11 Frame Exposure Timing Specifications
- OV2640 Light Response
- Register Set
- Package Specifications
- Revision History
28 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006
OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™
O
mni ision
5D REG5D 00 RW
Register 5D
Bit[7:0]: AVGsel[7:0], 16-zone average weight option
5E REG5E 00 RW
Register 5E
Bit[7:0]: AVGsel[15:8], 16-zone average weight option
5F REG5F 00 RW
Register 5F
Bit[7:0]: AVGsel[23:16], 16-zone average weight option
60 REG60 00 RW
Register 60
Bit[7:0]: AVGsel[31:24], 16-zone average weight option
61 HISTO_LOW 80 RW Histogram Algorithm Low Level
62 HISTO_HIGH 90 RW Histogram Algorithm High Level
63-7E RSVD XX – Reserved
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
Table 13 Device Control Register List (when 0xFF = 01) (Sheet 7 of 7)
Address
(Hex)
Register
Name
Default
(Hex)
R/W Description