Datasheet

Register Set
Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 27
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31 HEDY 30 RW
HSYNC Position and Width, End Point LSB 8 bits
This register and REG2A[3:2] (0x2A) define HSYNC end position,
each LSB will shift HSYNC end by 2 pixel period
32 REG32
36 (UXGA),
09 (SVGA,
CIF)
RW
Common Control 32
Bit[7:6]: Pixel clock divide option
00: No effect on PCLK
01: No effect on PCLK
10: PCLK frequency divide by 2
11: PCLK frequency divide by 4
Bit[5:3]: Horizontal window end position 3 LSBs (8 MSBs in
register HREFEND[7:0] (0x18))
Bit[2:0]: Horizontal window start position 3 LSBs (8 MSBs in
register HREFST[7:0] (0x17))
33 RSVD XX – Reserved
34 ARCOM2 20 RW
Bit[7:3]: Reserved
Bit[2]: Zoom window horizontal start point
Bit[1:0]: Reserved
35-44 RSVD XX – Reserved
45 REG45 00 RW
Register 45
Bit[7:6]: AGC[9:8], AGC highest gain control
Bit[5:0]: AEC[15:10], AEC MSBs
46 FLL 00 RW
Frame Length Adjustment LSBs
Each bit will add 1 horizontal line timing in frame
47 FLH 00 RW
Frame Length Adjustment MSBs
Each bit will add 256 horizontal lines timing in frame
48 COM19 00 RW
Common Control 19
Bit[7:2]: Reserved
Bit[1:0]: Zoom mode vertical window start point 2 LSBs
49 ZOOMS 00 RW Zoom Mode Vertical Window Start Point 8 MSBs
4A RSVD XX – Reserved
4B COM22 20 RW
Common Control 22
Bit[7:0]: Flash light control
4C-4D RSVD XX – Reserved
4E COM25 00 RW
Common Control 25 - reserved for banding
Bit[7:6]: 50Hz Banding AEC 2 MSBs
Bit[5:4]: 60HZ Banding AEC 2 MSBs
Bit[3:0]: Reserved
4F BD50 CA RW 50Hz Banding AEC 8 LSBs
50 BD60 A8 RW 60Hz Banding AEC 8 LSBs
51-5C RSVD XX – Reserved
Table 13 Device Control Register List (when 0xFF = 01) (Sheet 6 of 7)
Address
(Hex)
Register
Name
Default
(Hex)
R/W Description