Datasheet
Table Of Contents
- General Description
- Features
- Ordering Information
- Applications
- Key Specifications
- Functional Description
- Figure 2 Functional Block Diagram
- Image Sensor Array
- Analog Amplifier
- 10-Bit A/D Converters
- Channel Balance
- Black Level Compensation
- Windowing
- Timing Generator and Control Logic
- Digital Signal Processor (DSP)
- Output Formatter
- Compression Engine
- Microcontroller
- SCCB Interface
- Strobe Mode
- Reset
- Power Down Mode
- Digital Video Port
- Pin Description
- Electrical Characteristics
- Timing Specifications
- Figure 13 SCCB Interface Timing Diagram
- Table 9 SCCB InterfaceTiming Specifications
- Figure 14 UXGA, SVGA, and CIF Line/Pixel Output Timing
- Table 10 Pixel Timing Specifications
- Figure 15 UXGA Frame Timing
- Figure 16 SVGA Frame Timing
- Figure 17 CIF Mode Frame Timing
- Figure 18 Frame Exposure Mode Timing with EXPST_B Staying Low
- Figure 19 Frame Exposure Mode Timing with EXPST_B Asserted
- Table 11 Frame Exposure Timing Specifications
- OV2640 Light Response
- Register Set
- Package Specifications
- Revision History
26 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006
OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™
O
mni ision
24 AEW 78 RW
Luminance Signal High Range for AEC/AGC Operation
AEC/AGC values will decrease in auto mode when average luminance
is greater than AEW[7:0]
25 AEB 68 RW
Luminance Signal Low Range for AEC/AGC Operation
AEC/AGC values will increase in auto mode when average luminance
is less than AEB[7:0]
26 VV D4 RW
Fast Mode Large Step Range Threshold - effective only in AEC/AGC
fast mode (COM8[7] = 1)
Bit[7:4]: High threshold
Bit[3:0]:Low threshold
Note: AEC/AGC may change in larger steps when luminance average
is greater than VV[7:4] or less than VV[3:0].
27-29 RSVD XX – Reserved
2A REG2A 00 RW
Register 2A
Bit[7:4]: Line interval adjust value 4 MSBs (LSBs in FRARL[7:0]
(0x2B))
Bit[3:2]: HSYNC timing end point adjustment MSB 2 bits
(LSBs in register HEDY[7:0] (0x31))
Bit[1:0]: HSYNC timing start point adjustment MSB 2 bits
(LSBs in register HSDY[7:0] (0x30))
2B FRARL 00 RW
Line Interval Adjustment Value LSB 8 bits (MSBs in REG2A[7:4]
(0x2A))
The frame rate will be adjusted by changing the line interval. Each LSB
will add 1/1922 T
frame
in UXGA and 1/1190 T
frame
in SVGA mode to te
frame period.
2C RSVD XX – Reserved
2D ADDVSL 00 RW
VSYNC Pulse Width LSB 8 bits
Bit[7:0]: Line periods added to VSYNC width. Default VSYNC
output width is 4 x t
line
. Each LSB count will add 1 x t
line
to the VSYNC active period.
2E ADDVSH 00 RW
VSYNC Pulse Width MSB 8 bits
Bit[7:0]: Line periods added to VSYNC width. Default VSYNC
output width is 4 x t
line
. Each MSB count will add
256 x t
line
to the VSYNC active period.
2F YAVG 00 RW
Luminance Average (this register will auto update)
Average Luminance is calculated from the B/Gb/Gr/R channel average
as follows:
B/Gb/Gr/R channel average =
(BAVG[7:0] + (2 x GbAVG[7:0]) + RAVG[7:0]) x 0.25
30 HSDY 08 RW
HSYNC Position and Width, Start Point LSB 8 bits
This register and REG2A[1:0] (0x2A) define HSYNC start position,
each LSB will shift HSYNC start by 2 pixel period
Table 13 Device Control Register List (when 0xFF = 01) (Sheet 5 of 7)
Address
(Hex)
Register
Name
Default
(Hex)
R/W Description