Datasheet

Register Set
Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 25
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15 COM10 00 RW
Common Control 10 (if Bypass DSP is selected)
Bit[7]: CHSYNC pin output swap
0: CHSYNC
1: HREF
Bit[6]: HREF pin output swap
0: HREF
1: CHSYNC
Bit[5]: PCLK output selection
0: PCLK always output
1: PCLK output qualified by HREF
Bit[4]: PCLK edge selection
0: Data is updated at the falling edge of PCLK (user
can latch data at the next rising edge of PCLK)
1: Data is updated at the rising edge of PCLK (user can
latch data at the next falling edge of PCLK)
Bit[3]: HREF output polarity
0: Output positive HREF
1: Output negative HREF, HREF negative for data
valid
Bit[2]: Reserved
Bit[1]: VSYNC polarity
0: Positive
1: Negative
Bit[0]: HSYNC polarity
0: Positive
1: Negative
16 RSVD XX – Reserved
17 HREFST 11 RW
Horizontal Window Start MSB 8 bits (3 LSBs in REG32[2:0] (0x32))
Bit[10:0]: Selects the start of the horizontal window, each LSB
represents two pixels
18 HREFEND
75 (UXGA),
43 (SVGA,
CIF)
RW
Horizontal Window End MSB 8 bits (3 LSBs in REG32[5:3] (0x32))
Bit[10:0]: Selects the end of the horizontal window, each LSB
represents two pixels
19 VSTRT
01 (UXGA),
00 (SVGA,
CIF)
RW
Vertical Window Line Start MSB 8 bits (2 LSBs in COM1[1:0] (0x03))
Bit[9:0]: Selects the start of the vertical window, each LSB
represents two scan lines.
1A VEND 97 RW
Vertical Window Line End MSB 8 bits (2 LSBs in COM1[3:2] (0x03))
Bit[9:0]: Selects the end of the vertical window, each LSB
represents two scan lines.
1B RSVD XX – Reserved
1C MIDH 7F R Manufacturer ID Byte – High (Read only = 0x7F)
1D MIDL A2 R Manufacturer ID Byte – Low (Read only = 0xA2)
1E-23 RSVD XX – Reserved
Table 13 Device Control Register List (when 0xFF = 01) (Sheet 4 of 7)
Address
(Hex)
Register
Name
Default
(Hex)
R/W Description