Datasheet
Table Of Contents
- General Description
- Features
- Ordering Information
- Applications
- Key Specifications
- Functional Description
- Figure 2 Functional Block Diagram
- Image Sensor Array
- Analog Amplifier
- 10-Bit A/D Converters
- Channel Balance
- Black Level Compensation
- Windowing
- Timing Generator and Control Logic
- Digital Signal Processor (DSP)
- Output Formatter
- Compression Engine
- Microcontroller
- SCCB Interface
- Strobe Mode
- Reset
- Power Down Mode
- Digital Video Port
- Pin Description
- Electrical Characteristics
- Timing Specifications
- Figure 13 SCCB Interface Timing Diagram
- Table 9 SCCB InterfaceTiming Specifications
- Figure 14 UXGA, SVGA, and CIF Line/Pixel Output Timing
- Table 10 Pixel Timing Specifications
- Figure 15 UXGA Frame Timing
- Figure 16 SVGA Frame Timing
- Figure 17 CIF Mode Frame Timing
- Figure 18 Frame Exposure Mode Timing with EXPST_B Staying Low
- Figure 19 Frame Exposure Mode Timing with EXPST_B Asserted
- Table 11 Frame Exposure Timing Specifications
- OV2640 Light Response
- Register Set
- Package Specifications
- Revision History
Register Set
Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 23
O
mni ision
0C COM3 38 RW
Common Control 3
Bit[7:3]: Reserved
Bit[2]: Set banding manually
0: 60 Hz
1: 50 Hz
Bit[1]: Auto set banding
Bit[0]: Snapshot option
0: Enable live video output after snapshot sequence
1: Output single frame only
0D COM4 07 RW
Common Control 4
Bit[7:3]: Reserved
Bit[2]: Clock output power-down pin status
0: Tri-state data output pin upon power-down
1: Data output pin hold at last state before power-down
Bit[1:0]: Reserved
0E-0F RSVD XX – Reserved
10 AEC 33 RW
Automatic Exposure Control 8 bits for AEC[9:2] (AEC[15:10] is in
register REG45[5:0] (0x45), AEC[1:0] is in register REG04[1:0] (0x04))
AEC[15:0]: Exposure time
T
EX
= t
LINE
x AEC[15:0]
Note: The maximum exposure time is 1 frame period even if TEX is
longer than 1 frame period.
11 CLKRC 00 RW
Clock Rate Control
Bit[7]: Internal frequency doublers ON/OFF selection
0: OFF
1: ON
Bit[6]: Reserved
Bit[5:0]: Clock divider
CLK = XVCLK/(decimal value of CLKRC[5:0] + 1)
Table 13 Device Control Register List (when 0xFF = 01) (Sheet 2 of 7)
Address
(Hex)
Register
Name
Default
(Hex)
R/W Description