Datasheet
Table Of Contents
- General Description
- Features
- Ordering Information
- Applications
- Key Specifications
- Functional Description
- Figure 2 Functional Block Diagram
- Image Sensor Array
- Analog Amplifier
- 10-Bit A/D Converters
- Channel Balance
- Black Level Compensation
- Windowing
- Timing Generator and Control Logic
- Digital Signal Processor (DSP)
- Output Formatter
- Compression Engine
- Microcontroller
- SCCB Interface
- Strobe Mode
- Reset
- Power Down Mode
- Digital Video Port
- Pin Description
- Electrical Characteristics
- Timing Specifications
- Figure 13 SCCB Interface Timing Diagram
- Table 9 SCCB InterfaceTiming Specifications
- Figure 14 UXGA, SVGA, and CIF Line/Pixel Output Timing
- Table 10 Pixel Timing Specifications
- Figure 15 UXGA Frame Timing
- Figure 16 SVGA Frame Timing
- Figure 17 CIF Mode Frame Timing
- Figure 18 Frame Exposure Mode Timing with EXPST_B Staying Low
- Figure 19 Frame Exposure Mode Timing with EXPST_B Asserted
- Table 11 Frame Exposure Timing Specifications
- OV2640 Light Response
- Register Set
- Package Specifications
- Revision History
22 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006
OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™
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Table 13 Device Control Register List (when 0xFF = 01) (Sheet 1 of 7)
Address
(Hex)
Register
Name
Default
(Hex) R/W Description
00 GAIN 00 RW
AGC Gain Control LSBs
Bit[7:0]: Gain setting
• Range: 1x to 32x
Gain =(Bit[7]+1) x (Bit[6]+1) x (Bit[5]+1) x (Bit[4]+1) x (1+Bit[3:0]/16)
Note: Set COM8[2] = 0 to disable AGC.
01-02 RSVD XX – Reserved
03 COM1
0F (UXGA)
0A (SVGA),
06 (CIF)
RW
Common Control 1
Bit[7:6]: Dummy frame control
00: Reserved
01: Allow 1 dummy frame
10: Allow 3 dummy frames
11: Allow 7 dummy frames
Bit[5:4]: Reserved
Bit[3:2]: Vertical window end line control 2 LSBs
(8 MSBs in VEND[7:0] (0x1A))
Bit[1:0]: Vertical window start line control 2 LSBs
(8 MSBs in VSTRT[7:0] (0x19))
04 REG04 20 RW
Register 04
Bit[7]: Horizontal mirror
Bit[6]: Vertical flip
Bit[4]: VREF bit[0]
Bit[3]: HREF bit[0]
Bit[2]: Reserved
Bit[1:0]: AEC[1:0]
(AEC[15:10] is in register REG45[5:0] (0x45),
AEC[9:2] is in register AEC[7:0] (0x10))
05-07 RSVD XX – Reserved
08 REG08 40 RW Frame Exposure One-pin Control Pre-charge Row Number
09 COM2 00 RW
Common Control 2
Bit[7:5]: Reserved
Bit[4]: Standby mode enable
0: Normal mode
1: Standby mode
Bit[3]: Reserved
Bit[2]: Pin PWDN/RESETB used as SLVS/SLHS
Bit[1:0]: Output drive select
00: 1x capability
01: 3x capability
10: 2x capability
11: 4x capability
0A PIDH 26 R Product ID Number MSB (Read only)
0B PIDL 41 R Product ID Number LSB (Read only)