Datasheet

Table Of Contents
18 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006
OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP
O
mni ision
Register Set
Table 12 and Table 13 provides a list and description of the Device Control registers contained in the OV2640. For all register
Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 60 for write and 61 for read.
There are two different sets of register banks. Register 0xFF controls which set is accessible. When register 0xFF=00,
Table 12 is effective. When register 0xFF=01, Table 13 is effective.
Table 12 Device Control Register List (when 0xFF = 00) (Sheet 1 of 4)
Address
(Hex)
Register
Name
Default
(Hex) R/W Description
00-04 RSVD XX Reserved
05 R_BYPASS 0x1 RW
Bypass DSP
Bit[7:1]: Reserved
Bit[0]: Bypass DSP select
0: DSP
1: Bypass DSP, sensor out directly
06-43 RSVD XX Reserved
44 Qs 0C RW Quantization Scale Factor
45-4F RSVD XX Reserved
50 CTRLl[7:0] 00 RW
Bit[7]: LP_DP
Bit[6]: Round
Bit[5:3]: V_DIVIDER
Bit[2:0]: H_DIVIDER
51 HSIZE[7:0] 40 RW H_SIZE[7:0] (real/4)
52 VSIZE[7:0] F0 RW V_SIZE[7:0] (real/4)
53 XOFFL[7:0] 00 RW OFFSET_X[7:0]
54 YOFFL[7:0] 00 RW OFFSET_Y[7:0]
55 VHYX[7:0] 08 RW
Bit[7]: V_SIZE[8]
Bit[6:4]: OFFSET_Y[10:8]
Bit[3]: H_SIZE[8]
Bit[2:0]: OFFSET_X[10:8]
56 DPRP[7:0] 00 RW
Bit[7:4]: DP_SELY
Bit[3:0]: DP_SELX
57 TEST[3:0] 00 RW
Bit[7]: H_SIZE[9]
Bit[6:0]: Reserved
5A ZMOW[7:0] 58 RW OUTW[7:0] (real/4)
5B ZMOH[7:0] 48 RW OUTH[7:0] (real/4)
5C ZMHH[1:0] 00 RW
Bit[7:4]: ZMSPD (zoom speed)
Bit[2]: OUTH[8]
Bit[1:0]: OUTW[9:8]
5D-7B RSVD XX Reserved
7C BPADDR[3:0] 00 RW SDE Indirect Register Access: Address