Datasheet

ManualsBrandsM5Stack ManualsData Communication and Human Input DevicesPoE Camera w/o Wi-Fi (OV2640)

Table Of Contents

Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 1

Advanced Information

Preliminary Datasheet

OV2640 Color CMOS UXGA (2.0 MegaPixel) CAMERACHIP

mni ision

with OmniPixel2

Technology

General Description

The OV2640 CAMERACHIP

is a low voltage CMOS image

sensor that provides the full functionality of a single-chip

UXGA (1632x1232) camera and image processor in a small

footprint package. The OV2640 provides full-frame,

sub-sampled, scaled or windowed 8-bit/10-bit images in a

wide range of formats, controlled through the Serial Camera

Control Bus (SCCB) interface.

This product has an image array capable of operating at up

to 15 frames per second (fps) in UXGA resolution with

complete user control over image quality, formatting and

output data transfer. All required image processing functions,

including exposure control, gamma, white balance, color

saturation, hue control, white pixel canceling, noise

canceling, and more, are also programmable through the

SCCB interface. The OV2640 also includes a compression

engine for increased processing power. In addition,

OmniVision C

AMERACHIPS use proprietary sensor technology

to improve image quality by reducing or eliminating common

lighting/electrical sources of image contamination, such as

fixed pattern noise, smearing, etc., to produce a clean, fully

stable color image.

Features

• High sensitivity for low-light operation

• Low operating voltage for embedded portable apps

• Standard SCCB interface

• Output support for Raw RGB, RGB (RGB565/555),

GRB422, YUV (422/420) and YCbCr (4:2:2) formats

• Supports image sizes: UXGA, SXGA, SVGA, and any

size scaling down from SXGA to 40x30

•VarioPixel

method for sub-sampling

• Automatic image control functions including Automatic

Exposure Control (AEC), Automatic Gain Control

(AGC), Automatic White Balance (AWB), Automatic

Band Filter (ABF), and Automatic Black-Level

Calibration (ABLC)

• Image quality controls including color saturation,

gamma, sharpness (edge enhancement), lens

correction, white pixel canceling, noise canceling, and

50/60 Hz luminance detection

• Line optical black level output capability

• Video or snapshot operation

• Zooming, panning, and windowing functions

• Internal/external frame synchronization

• Variable frame rate control

• Supports LED and flash strobe mode

• Supports scaling

• Supports compression

• Embedded microcontroller

Ordering Information

Note: The OV2640 uses a lead-free

package.

Product Package

OV02640-VL9A (Color, lead-free) 38-pin CSP2

Applications

• Cellular and Camera Phones

•Toys

• PC Multimedia

• Digital Still Cameras

Key Specifications

Figure 1 OV2640 Pin Diagram (Top View)

Array Size UXGA 1600 x 1200

Power Supply

Core 1.2VDC +

Analog 2.5 ~ 3.0VDC

I/O 1.7V to 3.3V

Power

Requirements

Active

125 mW (for 15 fps, UXGA

YUV mode)

140 mW (for 15 fps, UXGA

compressed mode)

Standby 600 µA

Temperature

Range

Operation -30°C to 70°C

Stable Image 0°C to 50°C

Output Formats (8-bit)

• YUV(422/420)/YCbCr422

• RGB565/555

• 8-bit compressed data

• 8-/10-bit Raw RGB data

Lens Size 1/4"

Chief Ray Angle 25° non-linear

Maximum

Image

Transfer Rate

UXGA/SXGA 15 fps

SVGA 30 fps

CIF 60 fps

Sensitivity 0.6 V/Lux-sec

S/N Ratio 40 dB

Dynamic Range 50 dB

Scan Mode Progressive

Maximum Exposure Interval 1247 x t

ROW

Gamma Correction Programmable

Pixel Size 2.2 µm x 2.2 µm

Dark Current 15 mV/s at 60°C

Well Capacity 12 Ke

Fixed Pattern Noise <1% of V

PEAK-TO-PEAK

Image Area 3590 µm x 2684 µm

Package Dimensions 5725 µm x 6285 µm

OV2640

AGND SGND VREFN STROBE

A2 A4

A5 A6

B2 B4

B5 B6

C2 C4

C5 C6

D2 D6

E2 E4

E5 E6

F2 F4

F5 F6

G2 G4

G5 G6

DOGND EXPST_B

AVDD SVDD SVDD PWDNDOVDD FREX

HREF XVCLK VREFH RESETBSIO_D SIO_C

NCVSYNC

PCLK EGND Y6 DGNDY1 Y0

Y2 Y4 Y8 DVDDEVDD DVDD

Y3 Y5 Y7 Y9EVDD DGND

Summary of content (43 pages)

PAGE 1
Omni ision Advanced Information Preliminary Datasheet ® OV2640 Color CMOS UXGA (2.0 MegaPixel) CAMERACHIPTM with OmniPixel2TM Technology General Description Applications The OV2640 CAMERACHIPTM is a low voltage CMOS image sensor that provides the full functionality of a single-chip UXGA (1632x1232) camera and image processor in a small footprint package.
PAGE 2
OV2640 Omni Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ ision Functional Description Figure 2 shows the functional block diagram of the OV2640 image sensor.
PAGE 3
Omni ision Functional Description Image Sensor Array 10-Bit A/D Converters The OV2640 sensor has an image array of 1632 columns by 1232 rows (2,010,624 pixels). Figure 3 shows a cross-section of the image sensor array.
PAGE 4
OV2640 Omni Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ Figure 4 Windowing ision CIF Mode Column Start Column End HREF R Column o w The OV2640 can also operate at a higher frame rate to output 400 x 296 sized images. Figure 6 shows the sub-sampling diagram in both horizontal and vertical directions for CIF mode.
PAGE 5
Omni ision Functional Description output, the OV2640 will output continuous live video data unless in single frame transfer mode. Figure 18 and Figure 19 show the detailed timing and Table 11 shows the timing specifications for this mode. Output Formatter This block controls all output and data formatting required prior to sending the image out.
PAGE 6
OV2640 Omni Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ "1" and the OV2640 will use PWDN and RESETB pins as vertical and horizontal synchronization triggers supplied by a master device. The master device must provide the following signals: 1. System clock MCLK to XVCLK pin 2. Horizontal sync MHSYNC to RESETB pin 3. Vertical frame sync MVSYNC to PWDN pin See Figure 8 for slave mode connections and Figure 9 for detailed timing considerations.
PAGE 7
Omni ision Functional Description Line/Pixel Timing Pixel Output Pattern The OV2640 digital video port can be programmed to work in either master or slave mode. Table 2 shows the output data order from the OV2640. The data output sequence following the first HREF and after VSYNC is: B0,0 G0,1 B0,2 G0,3… B0,1598 G0,1599. After the second HREF the output is G1,0 R1,1 G1,2 R1,3… G1,1598 R1,1599…, etc.
PAGE 8
OV2640 Omni Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ ision Pin Description Table 3 Pin Description Pin Location A1 8 Name DOGND Pin Type Ground Input Function/Description Ground for digital video port Snapshot Exposure Start Trigger 0: Sensor starts exposure (only effective in snapshot mode) 1: Sensor stays in reset mode Note: There is no internal pull-up/pull-down resistor.
PAGE 9
Omni ision Table 3 Pin Description Pin Description Pin Location Name Pin Type Function/Description E2 Y0 I/O Video port output bit[0] Default: Input Note: There is no internal pull-up/pull-down resistor. E3 PCLK I/O Pixel clock output Default: Input Note: There is no internal pull-up/pull-down resistor.
PAGE 10
OV2640 Omni Color CMOS UXGA (2.
PAGE 11
Omni ision Electrical Characteristics Electrical Characteristics Table 5 Absolute Maximum Ratings Ambient Storage Temperature Supply Voltages (with respect to Ground) -40ºC to +95ºC VDD-A 4.5V VDD-C 3V VDD-IO 4.5V All Input/Output Voltages (with respect to Ground) -0.
PAGE 12
OV2640 Table 7 Omni Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ ision AC Characteristics (TA = 25°C, VDD-A = 2.8V) Symbol Parameter Min Typ Max Unit ADC Parameters B Analog bandwidth 20 MHz DLE DC differential linearity error 0.
PAGE 13
Omni ision Timing Specifications Timing Specifications Figure 13 SCCB Interface Timing Diagram tF t HIGH tR t HD:DAT t SU:DAT t LOW SIOC t SU:STA t HD:STA tSU:STO SIOD IN t BUF tAA t DH SIOD OUT Table 9 SCCB InterfaceTiming Specifications Symbol Parameter Min Typ Max Unit 400 KHz fSIO_C Clock Frequency tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 600 ns tAA SIOC low to Data Out valid 100 tBUF Bus free time before new START 1.
PAGE 14
OV2640 Omni Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ ision Figure 14 UXGA, SVGA, and CIF Line/Pixel Output Timing tp t pr t pf PCLK or MCLK t dphf t dphr HREF t hd t su D[9:0] P1599/799/399 Invalid Data P0 P1 P2 P 1598/798/398 P1599/799/399 t dpd Table 10 Pixel Timing Specifications Symbol 14 Parameter tp PCLK period tpr Min Typ Max Unit 27.78 ns PCLK rising time 3.5 ns tpf PCLK falling time 2.
PAGE 15
Omni ision Timing Specifications Figure 15 UXGA Frame Timing 1248 x tLINE VSYNC 4 x tLINE 27193 tP tLINE = 1922 tP 57697 tP 322 tP HREF 1600 tP 189 tP 80 tP HSYNC D[9:0] Invalid Data P0 - P1599 Row 0 Row 1 Row 2 Row 1199 Figure 16 SVGA Frame Timing 672 x tLINE VSYNC 4 x tLINE 7415 tP tLINE = 1190 tP 73895 tP 390 tP HREF 800 tP 179 tP 80 tP HSYNC D[9:0] Invalid Data P0 - P799 Row 0 Row 1 Row 2 Row 599 Figure 17 CIF Mode Frame Timing 336 x tLINE VSYNC 3707.
PAGE 16
OV2640 Omni Color CMOS UXGA (2.
PAGE 17
Omni ision Timing Specifications OV2640 Light Response Figure 20 OV2640 Light Response OV-9620spectrum response OV2640 Spectrum Response 200 180 160 Sensitivity 140 120 100 80 60 40 20 1180nm 1100nm 1060nm 1020nm 980nm 940nm 900nm 860nm 820nm 780nm 740nm 700nm 660nm 620nm 580nm 540nm 500nm 460nm 420nm 380nm 300nm 0 Wavelength R Version 1.
PAGE 18
OV2640 Omni Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ ision Register Set Table 12 and Table 13 provides a list and description of the Device Control registers contained in the OV2640. For all register Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 60 for write and 61 for read. There are two different sets of register banks. Register 0xFF controls which set is accessible. When register 0xFF=00, Table 12 is effective.
PAGE 19
Omni ision Table 12 Register Set Device Control Register List (when 0xFF = 00) (Sheet 2 of 4) Address (Hex) Register Name Default (Hex) R/W 7D BPDATA[7:0] 00 RW 7E-85 RSVD XX – Description SDE Indirect Register Access: Data Reserved Module Enable 86 CTRL2 0D RW Bit[7:6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Reserved DCW SDE UV_ADJ UV_AVG Reserved CMX Module Enable Bit[7]: Bit[6]: Bit[5:0]: BPC WPC Reserved 87 CTRL3 50 RW 88-8B RSVD XX – 8C SIZEL[5:0] 00 RW 8D
PAGE 20
OV2640 Table 12 Address (Hex) Omni Color CMOS UXGA (2.
PAGE 21
Omni ision Table 12 Address (Hex) Register Set Device Control Register List (when 0xFF = 00) (Sheet 4 of 4) Register Name Default (Hex) R/W Description SCCB Slave Control F8 F9 SS_CTRL 01 MC_BIST RW RW Bit[7:6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Reserved Address auto-increase enable Reserved SCCB enable Delay SCCB master clock Enable SCCB master access Enable sensor pass through access Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Microcontroller Reset Boot ROM sele
PAGE 22
OV2640 Table 13 Address (Hex) Omni Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ ision Device Control Register List (when 0xFF = 01) (Sheet 1 of 7) Register Name Default (Hex) R/W Description AGC Gain Control LSBs Bit[7:0]: 00 GAIN 00 RW 01-02 RSVD XX – Gain setting • Range: 1x to 32x Gain = (Bit[7]+1) x (Bit[6]+1) x (Bit[5]+1) x (Bit[4]+1) x (1+Bit[3:0]/16) Note: Set COM8[2] = 0 to disable AGC.
PAGE 23
Omni ision Table 13 Address (Hex) Register Set Device Control Register List (when 0xFF = 01) (Sheet 2 of 7) Register Name Default (Hex) R/W Description Common Control 3 Bit[7:3]: Bit[2]: 0C COM3 38 RW Bit[1]: Bit[0]: Reserved Set banding manually 0: 60 Hz 1: 50 Hz Auto set banding Snapshot option 0: Enable live video output after snapshot sequence 1: Output single frame only Common Control 4 0D COM4 07 RW Bit[7:3]: Bit[2]: Bit[1:0]: 0E-0F RSVD XX – Reserved Clock output power-down pin
PAGE 24
OV2640 Table 13 Address (Hex) Omni Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ ision Device Control Register List (when 0xFF = 01) (Sheet 3 of 7) Register Name Default (Hex) R/W Description Common Control 7 Bit[7]: Bit[6:4]: 12 COM7 00 RW Bit[3]: Bit[2]: Bit[1]: Bit[0]: SRST 1: Initiates system reset.
PAGE 25
Omni ision Table 13 Address (Hex) Register Set Device Control Register List (when 0xFF = 01) (Sheet 4 of 7) Register Name Default (Hex) R/W Description Common Control 10 (if Bypass DSP is selected) Bit[7]: Bit[6]: Bit[5]: Bit[4]: 15 COM10 00 RW Bit[3]: Bit[2]: Bit[1]: Bit[0]: CHSYNC pin output swap 0: CHSYNC 1: HREF HREF pin output swap 0: HREF 1: CHSYNC PCLK output selection 0: PCLK always output 1: PCLK output qualified by HREF PCLK edge selection 0: Data is updated at the falling edge of
PAGE 26
OV2640 Table 13 Omni Color CMOS UXGA (2.
PAGE 27
Omni ision Table 13 Register Set Device Control Register List (when 0xFF = 01) (Sheet 6 of 7) Address (Hex) Register Name Default (Hex) R/W 31 HEDY 30 RW Description HSYNC Position and Width, End Point LSB 8 bits This register and REG2A[3:2] (0x2A) define HSYNC end position, each LSB will shift HSYNC end by 2 pixel period Common Control 32 Bit[7:6]: 32 REG32 36 (UXGA), 09 (SVGA, CIF) RW Bit[5:3]: Bit[2:0]: Pixel clock divide option 00: No effect on PCLK 01: No effect on PCLK 10: PCLK frequ
PAGE 28
OV2640 Table 13 Omni Color CMOS UXGA (2.
PAGE 29
Omni ision Package Specifications Package Specifications The OV2640 uses a 38-ball Chip Scale Package 2 (CSP2). Refer to Figure 11 for package information, Table 9 for package dimensions and Figure 12 for the array center on the chip. Note: For OVT devices that are lead-free, all part marking letters are lower case. Underlining the last digit of the lot number indicates CSP2 is used.
PAGE 30
OV2640 Omni Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ ision Sensor Array Center Figure 22 OV2640 Sensor Array Center A1 A2 A3 A4 A5 A6 A rray C enter (469.6 μm, 145 μm) 3590.4 μm 2684 μm S ens or A rray OV 2640 P ac kage C enter (0, 0) T op V iew NOT E S : 1. T his drawing is not to s cale and is for reference only. 2. As mos t optical as s emblies invert and mirror the image, the chip is typically mounted with pins A1 to A6 oriented down on the P C B .
PAGE 31
Omni ision Package Specifications IR Reflow Ramp Rate Requirements OV2640 Lead-Free Packaged Devices Note: For OVT devices that are lead-free, all part marking letters are lower case Figure 23 IR Reflow Ramp Rate Requirements 300.0 Z1 Z2 Z3 Z4 Z5 Z6 Z7 end 280.0 260.0 240.0 220.0 Temperature ( C ) 200.0 180.0 160.0 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0.0 0.0 -22 -2 0.6 18 38 1.1 58 78 1.6 98 118 2.2 138 158 2.8 178 198 3.3 218 238 258 3.
PAGE 32
OV2640 Omni Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™ ision Note: • All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation. • OmniVision Technologies, Inc.
PAGE 33
Omni ision TM REVISION CHANGE LIST Document Title: OV2640 Datasheet Version: 1.
PAGE 34
Omni ision TM REVISION CHANGE LIST Document Title: OV2640 Datasheet Version: 1.01 DESCRIPTION OF CHANGES The following changes were made to version 1.0: • Under Key Specifications on page 1, changed specification for Core Power Supply from “1.2VDC + 10%” to “1.2VDC + 5%” • Under Key Specifications on page 1, changed specification for Analog Power Supply from “2.8VDC + 10%” to “2.5 ~ 3.0VDC” • Under Key Specifications on page 1, changed specification for I/O Power Supply from “1.8V to 3.3V” to “1.
PAGE 35
Omni ision TM REVISION CHANGE LIST Document Title: OV2640 Datasheet Version: 1.1 DESCRIPTION OF CHANGES The following changes were made to version 1.
PAGE 36
Omni ision TM DESCRIPTION OF CHANGES (CONTINUED) • • • • In Figure 21 on page 28, changed callout C3 to measure from thickness of glass and added callout C4 to measure airgap from glass to die.
PAGE 37
Omni ision TM REVISION CHANGE LIST Document Title: OV2640 Datasheet Version: 1.2 DESCRIPTION OF CHANGES The following changes were made to version 1.
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Omni ision TM REVISION CHANGE LIST Document Title: OV2640 Datasheet Version: 1.21 DESCRIPTION OF CHANGES The following changes were made to version 1.
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Omni ision TM REVISION CHANGE LIST Document Title: OV2640 Datasheet Version: 1.3 DESCRIPTION OF CHANGES The following changes were made to version 1.
PAGE 40
Omni ision TM DESCRIPTION OF CHANGES (CONTINUED) • In Table 1 on page 8, made the following changes/corrections: – Corrected pin type of pin F2 from Analog to Power and changed description to “Sensor digital power (Core)” – Added “Default: Input” and “Note: There is no internal pull-up/pull-down resistor” to description of pins F3, F4, and F5 – Corrected pin type of pin F6 from Analog to Power and changed description to be the same as pin F2 – Corrected pin type of pin G2 from Power to Ground – Added “D
PAGE 41
Omni ision TM REVISION CHANGE LIST Document Title: OV2640 Datasheet Version: 1.4 DESCRIPTION OF CHANGES The following changes were made to version 1.
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Omni ision TM REVISION CHANGE LIST Document Title: OV2640 Datasheet Version: 1.5 DESCRIPTION OF CHANGES The following changes were made to version 1.4: • Under Register Set section on page 18, changed the second paragraph from “There are two different sets for register address from 0x00 to 0x7E. Both register 0xF8 and register 0xFF control which set is accessible. When 0xF8=00 and 0xFF=00, Table 12 is effective. When 0xF8=01, 0xFF=7F, Table 13 is effective.
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Omni ision TM REVISION CHANGE LIST Document Title: OV2640 Datasheet Version: 1.6 DESCRIPTION OF CHANGES The following changes were made to version 1.