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3. FUNCTIONAL DESCRIPTION
This chapter describes the ESP32-S3 various modules and functions.
3.1. CPU AND MEMORY
Xtensa® dual-core 32-bit LX7 microprocessor,up to 240 MHz

384 KB ROM
 512 KB SRAM
 16 KB SRAM in RTC
 SPI, Dual SPI, Quad SPI, Octal SPI, QPI and OPI interfaces that allow connection to
multiple flash and external RAM
 Flash controller with cache is supported
 Flash in-Circuit Programming (ICP) is supported
3.2. STORAGE DESCRIPTION
3.2.1. External Flash and RAM
ESP32-S3 supports SPI, Dual SPI, Quad SPI, Octal SPI, QPI and OPI interfaces that allow
connection to multiple external flash and RAM.
The external flash and RAM can be mapped into the CPU instruction memory space
and read-only data memory space. The external RAM can also be mapped into the
CPU data memory space. ESP32-S3 supports up to 1GB of external flash and RAM, and
hardware encryption/decryption based on XTS-AES to protect users’programs and
data in flash and external RAM.
Through high-speed caches, ESP32-S3 can support at a time up to:
• External flash or RAM mapped into 32 MB instruction space as
individual blocks of 64 KB
• External RAM mapped into 32 MB data space as individual blocks of
64 KB. 8-bit, 16-bit, 32-bit, and 128-bit reads and writes are
supported. External flash can also be mapped into 32 MB data space
as individual blocks of 64 KB, but only supporting 8-bit, 16-bit, 32-
bit and 128-bit reads.
3.3. CPU CLOCK
The CPU clock has three possible sources: