Use Instructions

L710HG Hardware Design
25
Figure 3-8 L710HG to codec module timing
Table 3-10 (b) PCM interface Timing
Parameter Descriptions
DC characters
Min. Typ. Max. Unit
T(sync) PCM_SYNC cycle
- 125 - us
T(synch)
PCM_SYNC h
igh level hold
time
- 488 - ns
T(syncl)
PCM_SYNC l
ow level hold
time
- 124.5 - us
T(clk) PCM_CLK cycle
- 488 - ns
T(clkh)
PCM_CLK h
igh level hold
time
- 244 - ns
T(clkl) PCM_CLK low level hold time
- 244 - ns
T(susync) PCM_SYNC establish time
- 122 - ns
T(hsync) PCM_SYNC hold time
- 366 - ns
T(sudin) PCM_IN establish time
60 - - ns
T(hdin) PCM_IN hold time
60 - - ns
T(pdout)
From PCM_CLK rising edge
to
PCM_OUT valid time
- - 60 ns
T(zdout)
From PCM_CLK
falling edge
to PCM_OUT h
igh
impendence delay time
- - 60 ns
3.6.2 PCM interface application
L710HG only support the host mode, PCM_SYNC,PCM_CLK is the output pin，PCM_SYN as the
synchronizing output 8kHz sync signal. PCM Data support 8bit or 16bit data.