Data Sheet

22
LS001ONWAS Datasheet
7.1.3 SDIO Timing Data—Default-Speed/High-Speed Modes
Symbol
Parameter Condition Min Typ Max Units
fpp Clock frequency
Default-speed 0 -- 25 MHz
High-speed 0 -- 50 MHz
TWL Clock low time
Default-speed
10 -- -- ns
High-speed 7 -- -- ns
TWH Clock high time
Default-speed
10 -- -- ns
High-speed 7 -- -- ns
TISU Input setup time
Default-speed 5 -- -- ns
High-speed 6 -- -- ns
TIH Input hold time
Default-speed
5 -- -- ns
High-speed 2 -- -- ns
TODLY
Output delay time
CL ≤ 40 pF (1 card)
Default-speed
-- -- 14 ns
High-speed -- -- 14 ns
TOH Output hold time High-speed 2.5 -- -- ns
7.1.4 SDIO Timing Diagram—SDR12/SDR25/SDR50 Modes (up to 100 MHz) (1.8V)
SDIO Timing Diagram—SDR12, SDR25, SDR50 Modes (up to 100 MHz) (1.8V)
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